JPS5732162A - Information transmitter - Google Patents
Information transmitterInfo
- Publication number
- JPS5732162A JPS5732162A JP10854380A JP10854380A JPS5732162A JP S5732162 A JPS5732162 A JP S5732162A JP 10854380 A JP10854380 A JP 10854380A JP 10854380 A JP10854380 A JP 10854380A JP S5732162 A JPS5732162 A JP S5732162A
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- circuit
- data
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/12—Modulator circuits; Transmitter circuits
Abstract
PURPOSE:To obtain a clock frequency synchronized with demodulated data from a demodulation output, by performing ternary FSK modulation and by obtaining the clock frequency by detecting change points of a signal or inverting the signal. CONSTITUTION:Binary information 2a is read out from a storing circuit 2 with the clock 1a of an oscillator 1 and inputted to the synthesizing circuit 52 or 51 of a modulator 5. The data inputted to the synthesizing circuit 52 is synthesized together with the output 4a of the 2nd oscillator 4 and the output 1a of the oscillator 1 to obtain a frequency signal which corresponds to the output data 0 of the storing circuit 2. Similarly, a signal corresponding to the output data 1 of the circuit 2 is outputted from rhe synthesizing circuit 51. The output of the circuits 52 and 51 are synthesized by a synthesizing circuit 53; in part of a one-bit time, the resulting signal is sent out corresponding to the data of the storing circuit 2 and in the remaining time, neither frequency signal 51a nor 52a is sent out, thereby outputting a ternary output by demodulating an output 53a. A clock frequency is obtained by detecting change points of a signal or inverting a negative-side signal into positive- side one.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10854380A JPS5732162A (en) | 1980-08-04 | 1980-08-04 | Information transmitter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10854380A JPS5732162A (en) | 1980-08-04 | 1980-08-04 | Information transmitter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5732162A true JPS5732162A (en) | 1982-02-20 |
Family
ID=14487482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10854380A Pending JPS5732162A (en) | 1980-08-04 | 1980-08-04 | Information transmitter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5732162A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61189039A (en) * | 1985-02-16 | 1986-08-22 | Matsushita Electric Ind Co Ltd | Transmitting device for optical space |
-
1980
- 1980-08-04 JP JP10854380A patent/JPS5732162A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61189039A (en) * | 1985-02-16 | 1986-08-22 | Matsushita Electric Ind Co Ltd | Transmitting device for optical space |
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