JPS57212547A - Address conversion system - Google Patents

Address conversion system

Info

Publication number
JPS57212547A
JPS57212547A JP9781081A JP9781081A JPS57212547A JP S57212547 A JPS57212547 A JP S57212547A JP 9781081 A JP9781081 A JP 9781081A JP 9781081 A JP9781081 A JP 9781081A JP S57212547 A JPS57212547 A JP S57212547A
Authority
JP
Japan
Prior art keywords
address
stored
processor
data
adc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9781081A
Other languages
Japanese (ja)
Inventor
Masahide Kubo
Hitoshi Isobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9781081A priority Critical patent/JPS57212547A/en
Publication of JPS57212547A publication Critical patent/JPS57212547A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To shorten the data transfer time, by providing an address counter which uses address information, which is outputted to a date terminal from a processor, as the initial value and is counted up each time when the processor outputs a prescribed address to an address terminal. CONSTITUTION:When data of the first word is stored in a start address DA1 of a transfer destination region, address counters ADC-L and ADC-H are counted up by one, and their contents are set to an address DA2. Next, a processor CPU adds 1 to an address SA1 stored in an index register X to make an address SA2 and compares the last address SAN stored in a region END with the address DA2 stored in the index register X; and if they do not coincide with each other, the processor CPU executes the transfer of data TD2 of the second word from a step S18 by an instruction BNES18 in a step S22.
JP9781081A 1981-06-24 1981-06-24 Address conversion system Pending JPS57212547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9781081A JPS57212547A (en) 1981-06-24 1981-06-24 Address conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9781081A JPS57212547A (en) 1981-06-24 1981-06-24 Address conversion system

Publications (1)

Publication Number Publication Date
JPS57212547A true JPS57212547A (en) 1982-12-27

Family

ID=14202115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9781081A Pending JPS57212547A (en) 1981-06-24 1981-06-24 Address conversion system

Country Status (1)

Country Link
JP (1) JPS57212547A (en)

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