JPS5621244A - Data processing unit - Google Patents

Data processing unit

Info

Publication number
JPS5621244A
JPS5621244A JP9702579A JP9702579A JPS5621244A JP S5621244 A JPS5621244 A JP S5621244A JP 9702579 A JP9702579 A JP 9702579A JP 9702579 A JP9702579 A JP 9702579A JP S5621244 A JPS5621244 A JP S5621244A
Authority
JP
Japan
Prior art keywords
unit
information
address
prefetch
post
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9702579A
Other languages
Japanese (ja)
Inventor
Takeshi Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9702579A priority Critical patent/JPS5621244A/en
Publication of JPS5621244A publication Critical patent/JPS5621244A/en
Pending legal-status Critical Current

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  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To enable to give the compratively small size unit the advantage of information prefetch or post-writing processing, by providing the byte aligner circuit to the buffer register between the memory unit and the access request unit.
CONSTITUTION: Based on the content of the N sets of address registers 2 pointing out the present processing address, the prefetch address and/or post stored address production circuit 4 and memory unit 1 are provided and the prefetch of information or post writing of information processing is made with microprogram. In this data processor, the buffer register 5 storing a multiple byte of 2P bytes and the arrangement unit having byte aligner circuit 6 are taken as a pair and the pairs are provided by N sets corresponding to the register 2. Further, the information giving and reception between the memory unit 1 and the arranging unit pair is made in word unit and that between the arranging unit pair and the access request unit is made in the form of continuous information via the aligner circuit 6.
COPYRIGHT: (C)1981,JPO&Japio
JP9702579A 1979-07-30 1979-07-30 Data processing unit Pending JPS5621244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9702579A JPS5621244A (en) 1979-07-30 1979-07-30 Data processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9702579A JPS5621244A (en) 1979-07-30 1979-07-30 Data processing unit

Publications (1)

Publication Number Publication Date
JPS5621244A true JPS5621244A (en) 1981-02-27

Family

ID=14180878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9702579A Pending JPS5621244A (en) 1979-07-30 1979-07-30 Data processing unit

Country Status (1)

Country Link
JP (1) JPS5621244A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61211743A (en) * 1985-03-17 1986-09-19 Fujitsu Ltd Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61211743A (en) * 1985-03-17 1986-09-19 Fujitsu Ltd Information processor

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