JPS57206975A - Memory unit control circuit - Google Patents

Memory unit control circuit

Info

Publication number
JPS57206975A
JPS57206975A JP9180981A JP9180981A JPS57206975A JP S57206975 A JPS57206975 A JP S57206975A JP 9180981 A JP9180981 A JP 9180981A JP 9180981 A JP9180981 A JP 9180981A JP S57206975 A JPS57206975 A JP S57206975A
Authority
JP
Japan
Prior art keywords
unit
memory unit
control circuit
access
data block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9180981A
Other languages
Japanese (ja)
Other versions
JPS6112306B2 (en
Inventor
Isao Yamazaki
Kiyokazu Hanatani
Fumiaki Seto
Katsuhiro Matsukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9180981A priority Critical patent/JPS57206975A/en
Publication of JPS57206975A publication Critical patent/JPS57206975A/en
Publication of JPS6112306B2 publication Critical patent/JPS6112306B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To increase the access cycle efficiency of a memory unit, by producing address data to be fed to a memory unit in the next access cycle during the access cycle to the memory unit. CONSTITUTION:Access is given from each of the processing units 5-1-5-n to a memory unit 2 for each word and via a memory unit control circuit 1. The process of the whole device is controlled by a process controlling unit 4. Each of the units 5-1-5-n fetches a data block to be processed from the unit 2 based on an indication of the unit 4 and performs a process of data to store a data block of result into the unit 2. The address is preset to a register in a memory unit controlling circuit 1 from the unit 4 prior to the start of transfer of the data block in case access is given to the unit 2 from each of the units 5-1-5-n.
JP9180981A 1981-06-15 1981-06-15 Memory unit control circuit Granted JPS57206975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9180981A JPS57206975A (en) 1981-06-15 1981-06-15 Memory unit control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9180981A JPS57206975A (en) 1981-06-15 1981-06-15 Memory unit control circuit

Publications (2)

Publication Number Publication Date
JPS57206975A true JPS57206975A (en) 1982-12-18
JPS6112306B2 JPS6112306B2 (en) 1986-04-07

Family

ID=14036948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9180981A Granted JPS57206975A (en) 1981-06-15 1981-06-15 Memory unit control circuit

Country Status (1)

Country Link
JP (1) JPS57206975A (en)

Also Published As

Publication number Publication date
JPS6112306B2 (en) 1986-04-07

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