JPS57206056A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPS57206056A JPS57206056A JP8967981A JP8967981A JPS57206056A JP S57206056 A JPS57206056 A JP S57206056A JP 8967981 A JP8967981 A JP 8967981A JP 8967981 A JP8967981 A JP 8967981A JP S57206056 A JPS57206056 A JP S57206056A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- tab
- wire bonding
- pads
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE:To prevent faulty installation or connection by a method wherein the entire surface of a lead frame with its pellet mounting and wire bonding regions Ag plated is provided with a very thin protecting film of Ag. CONSTITUTION:A lead frame 1 is composed of a metal of Cu base and three leads 2 running in parallel with each other form a unit. The extremities of the leads 2 are formed larger than the other parts. the extremity of the central lead is a tab 6 accommodating a pellet 5. The extremities of the other side leads work as wire bonding pads 7. The primary surface of the tab 6 and pads 7 are plated with Ni and then with Ag, and the tab 6 forms a pellet installing region and the pads 7 wire bonding regions. The entire surface of the lead frame 1 is covered with protecting Ag film 12 so thin as to diffused into the lead frame base material when exposed to heat generated in a semiconductor device mounting process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8967981A JPS57206056A (en) | 1981-06-12 | 1981-06-12 | Lead frame |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8967981A JPS57206056A (en) | 1981-06-12 | 1981-06-12 | Lead frame |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57206056A true JPS57206056A (en) | 1982-12-17 |
Family
ID=13977438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8967981A Pending JPS57206056A (en) | 1981-06-12 | 1981-06-12 | Lead frame |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57206056A (en) |
-
1981
- 1981-06-12 JP JP8967981A patent/JPS57206056A/en active Pending
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