JPS57203130A - Data input controller - Google Patents
Data input controllerInfo
- Publication number
- JPS57203130A JPS57203130A JP56086854A JP8685481A JPS57203130A JP S57203130 A JPS57203130 A JP S57203130A JP 56086854 A JP56086854 A JP 56086854A JP 8685481 A JP8685481 A JP 8685481A JP S57203130 A JPS57203130 A JP S57203130A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- period
- information
- status change
- virtual input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/048—Monitoring; Safety
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Control By Computers (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To detect the status change of plant information in high speed, by executing the detection of fetching and its change of the status information of a plant with the hardware and providing a virtual input changed with a prescribed period. CONSTITUTION:When various control parameters are given from a computer program to a data input controller 5, the control for the fetching of information from an input module 6, operation of status change check and report to a main storage device 2 is made under the control of the device 5. On the status change table of the device 2, one bit reflecting the operating state of the device 5 is provided, a prescribed period is monitored with a built-in timer of the device 5, the timer is preset when the period is elapsed for a given time and the corresponding bit of the device 2 is set to 1. This bit is a bit representing the state of the device 5 and a virtual input to the program, and when this is at 1, the device 5 is in normal operating state. The virtual input bit is monitored with a monitoring period of the program longer than the monitor time period, and when this bit is at 0, the device 5 judge the state as failure to output alarm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56086854A JPS57203130A (en) | 1981-06-08 | 1981-06-08 | Data input controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56086854A JPS57203130A (en) | 1981-06-08 | 1981-06-08 | Data input controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57203130A true JPS57203130A (en) | 1982-12-13 |
JPH0234071B2 JPH0234071B2 (en) | 1990-08-01 |
Family
ID=13898394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56086854A Granted JPS57203130A (en) | 1981-06-08 | 1981-06-08 | Data input controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57203130A (en) |
-
1981
- 1981-06-08 JP JP56086854A patent/JPS57203130A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0234071B2 (en) | 1990-08-01 |
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