JPS57202148A - Code transmission system - Google Patents

Code transmission system

Info

Publication number
JPS57202148A
JPS57202148A JP56086605A JP8660581A JPS57202148A JP S57202148 A JPS57202148 A JP S57202148A JP 56086605 A JP56086605 A JP 56086605A JP 8660581 A JP8660581 A JP 8660581A JP S57202148 A JPS57202148 A JP S57202148A
Authority
JP
Japan
Prior art keywords
pulse
cmi
circuit
rule error
generates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56086605A
Other languages
Japanese (ja)
Inventor
Junichi Yugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56086605A priority Critical patent/JPS57202148A/en
Publication of JPS57202148A publication Critical patent/JPS57202148A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J99/00Subject matter not provided for in other groups of this subclass

Abstract

PURPOSE:To transmit analog information together with digital information, by generating one pulse to one CMI code rule error and reproducing the original analog signal by introducing the pulse train to a pulse frequency demodulation circuit. CONSTITUTION:An input analog signal 103 is converted into a PFM signal 123 at a modulator 105 at transmission side 50. An interface circuit 106 is operative with the leading of the signal 123 and generates only one pulse 121 with the CMI rule error with the same width as the period of a clock 102 synchronized with a data 101. A CMI coder 104 generates the CMI rule error only once to a transmission circuit 51 when this one pulse is received. At a reception side 52, a CMI composite circuit 114 detects the CMI code rule error and generates one CMI rule error detection pulse 122, and after the pulse width is adjusted with a monostable multivibrator circuit 116, the pulse is restored to the original analog signal 113 at a PFM demodulation circuit 115.
JP56086605A 1981-06-05 1981-06-05 Code transmission system Pending JPS57202148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56086605A JPS57202148A (en) 1981-06-05 1981-06-05 Code transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56086605A JPS57202148A (en) 1981-06-05 1981-06-05 Code transmission system

Publications (1)

Publication Number Publication Date
JPS57202148A true JPS57202148A (en) 1982-12-10

Family

ID=13891640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56086605A Pending JPS57202148A (en) 1981-06-05 1981-06-05 Code transmission system

Country Status (1)

Country Link
JP (1) JPS57202148A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51136224A (en) * 1975-05-21 1976-11-25 Hitachi Ltd Pulse transmission

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51136224A (en) * 1975-05-21 1976-11-25 Hitachi Ltd Pulse transmission

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