JPS57197644A - Data compressing device - Google Patents
Data compressing deviceInfo
- Publication number
- JPS57197644A JPS57197644A JP8109981A JP8109981A JPS57197644A JP S57197644 A JPS57197644 A JP S57197644A JP 8109981 A JP8109981 A JP 8109981A JP 8109981 A JP8109981 A JP 8109981A JP S57197644 A JPS57197644 A JP S57197644A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- peak
- max
- hold circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
Abstract
PURPOSE:To obtain a device that generates no blank space in its output signal even in a high frequency wave signal whose output is apt to be a singal-shot by applying sampling for it storing the max. value of the output signal for a sampling period through a peak-hold circuit. CONSTITUTION:It is arranged that sampling is applied to an input signal while storing its max. value for the sampling period through a peak-hold circuit. For instance, an input signal is subjected to branch input and converted into a mean value signal by a smoothing circuit 7. Then, a substractor circuit 8 combines the input signal 6 with the mean value signal from the smoothing circuit 7 and outputs a deviation signal which is applied to a peak-hold circuit 9. Next, the peak-hold circuit 9 converts the deviation signal into the max. value signal, with which an addor circuit 10 combines the mean value signal from the smoothing circuit 7 and outputs the result to an A/D convertor 11 through which it is converted into a digital signal and inputted to a computor 12.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8109981A JPS57197644A (en) | 1981-05-29 | 1981-05-29 | Data compressing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8109981A JPS57197644A (en) | 1981-05-29 | 1981-05-29 | Data compressing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57197644A true JPS57197644A (en) | 1982-12-03 |
Family
ID=13736931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8109981A Pending JPS57197644A (en) | 1981-05-29 | 1981-05-29 | Data compressing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57197644A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59201977A (en) * | 1983-04-28 | 1984-11-15 | Toyota Motor Corp | Controlling method of ignition timing of engine |
-
1981
- 1981-05-29 JP JP8109981A patent/JPS57197644A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59201977A (en) * | 1983-04-28 | 1984-11-15 | Toyota Motor Corp | Controlling method of ignition timing of engine |
JPH051394B2 (en) * | 1983-04-28 | 1993-01-08 | Toyota Motor Co Ltd |
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