JPS57195385A - Access circuit for dynamic memory - Google Patents

Access circuit for dynamic memory

Info

Publication number
JPS57195385A
JPS57195385A JP56078227A JP7822781A JPS57195385A JP S57195385 A JPS57195385 A JP S57195385A JP 56078227 A JP56078227 A JP 56078227A JP 7822781 A JP7822781 A JP 7822781A JP S57195385 A JPS57195385 A JP S57195385A
Authority
JP
Japan
Prior art keywords
selector
supplied
selection control
address information
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56078227A
Other languages
Japanese (ja)
Inventor
Yuji Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56078227A priority Critical patent/JPS57195385A/en
Publication of JPS57195385A publication Critical patent/JPS57195385A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To switch adress lines between page mode operation and refreshing operation through simple constitution, by performing the switching operation by a selector, a selection control circuit, and a gate circuit. CONSTITUTION:Memory address information and refresh address information from a processor 1 are supplied to a selector 3, and brought under the selection control of a selection control circuit 4 before being supplied to the address input of a dynamic memory 2. A signal with a logical level 0 and low-order address information are supplied to the 1st selection input A of the selector 3, and a signal with a logical level 1 and high-order address information are supplied to the 2nd selection input B, so that the selection control circuit 4 outputs the A or B selectively. The control circuit 4 generates a signal C for the selection control of the selector 3 on the basis of a memory request singal -MREQ, a refresh signal -RFSH, and a clock pulse phi.
JP56078227A 1981-05-23 1981-05-23 Access circuit for dynamic memory Pending JPS57195385A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56078227A JPS57195385A (en) 1981-05-23 1981-05-23 Access circuit for dynamic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56078227A JPS57195385A (en) 1981-05-23 1981-05-23 Access circuit for dynamic memory

Publications (1)

Publication Number Publication Date
JPS57195385A true JPS57195385A (en) 1982-12-01

Family

ID=13656157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56078227A Pending JPS57195385A (en) 1981-05-23 1981-05-23 Access circuit for dynamic memory

Country Status (1)

Country Link
JP (1) JPS57195385A (en)

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