JPS57187738A - Local network interface used within multi-station word processor system - Google Patents

Local network interface used within multi-station word processor system

Info

Publication number
JPS57187738A
JPS57187738A JP57068009A JP6800982A JPS57187738A JP S57187738 A JPS57187738 A JP S57187738A JP 57068009 A JP57068009 A JP 57068009A JP 6800982 A JP6800982 A JP 6800982A JP S57187738 A JPS57187738 A JP S57187738A
Authority
JP
Japan
Prior art keywords
network interface
local network
processor system
word processor
interface used
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57068009A
Other languages
English (en)
Inventor
Eru Ritoru Terensu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pitney Bowes Inc
Original Assignee
Pitney Bowes Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pitney Bowes Inc filed Critical Pitney Bowes Inc
Publication of JPS57187738A publication Critical patent/JPS57187738A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow
    • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • H04L49/9094—Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/376—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
JP57068009A 1981-04-22 1982-04-22 Local network interface used within multi-station word processor system Pending JPS57187738A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/256,332 US4441162A (en) 1981-04-22 1981-04-22 Local network interface with control processor & DMA controller for coupling data processing stations to common serial communications medium

Publications (1)

Publication Number Publication Date
JPS57187738A true JPS57187738A (en) 1982-11-18

Family

ID=22971852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57068009A Pending JPS57187738A (en) 1981-04-22 1982-04-22 Local network interface used within multi-station word processor system

Country Status (5)

Country Link
US (1) US4441162A (ja)
EP (1) EP0064347A1 (ja)
JP (1) JPS57187738A (ja)
AU (1) AU543489B2 (ja)
CA (1) CA1178355A (ja)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003053867A (ja) * 2001-08-09 2003-02-26 Dainippon Printing Co Ltd 複合された凹凸を有する積層体およびその製造方法、並びに金型の製造方法および成形品の成形方法

Also Published As

Publication number Publication date
AU543489B2 (en) 1985-04-18
EP0064347A1 (en) 1982-11-10
AU8284882A (en) 1982-10-28
US4441162A (en) 1984-04-03
CA1178355A (en) 1984-11-20

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