JPS57186892A - Digital line concentrating switch - Google Patents
Digital line concentrating switchInfo
- Publication number
- JPS57186892A JPS57186892A JP7163581A JP7163581A JPS57186892A JP S57186892 A JPS57186892 A JP S57186892A JP 7163581 A JP7163581 A JP 7163581A JP 7163581 A JP7163581 A JP 7163581A JP S57186892 A JPS57186892 A JP S57186892A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- gate
- time switch
- inputted
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Sub-Exchange Stations And Push- Button Telephones (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To independently execute local call processing of a line concentration stage, by providing a separating gate and a multiplexing gate on the output side of a time switch in the up direction and the input side of a time switch in the down direction, respectively. CONSTITUTION:As for a time switch of the up-side, a digital signal whose input multiplexing degree J is inputted to a service memory BFMF, and a digital signal of a channel J is outputted under the control of a control memory CTLMF. In accordance with this output signal, a channel K and a channel L are connected to the distribution stage side and a multiplexing gate GB of the down- side, respectively, by a separating gate GB. Gate control of the channels K, J is fixedly assigned by a counter CTR. On the other hand, as for a time switch of the down-side, the channel K is inputted from the distribution stage, is multiplexed with a channel L of the up-side switch by the gate GB, the channel J is inputted to the service memory BFMB, is switched by the control memory CTMB, and the channel J is outputted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7163581A JPS57186892A (en) | 1981-05-13 | 1981-05-13 | Digital line concentrating switch |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7163581A JPS57186892A (en) | 1981-05-13 | 1981-05-13 | Digital line concentrating switch |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57186892A true JPS57186892A (en) | 1982-11-17 |
Family
ID=13466301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7163581A Pending JPS57186892A (en) | 1981-05-13 | 1981-05-13 | Digital line concentrating switch |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57186892A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6076890A (en) * | 1983-10-03 | 1985-05-01 | Nec Corp | Line concentration channel system |
JPS60143048A (en) * | 1983-12-29 | 1985-07-29 | Nec Corp | Line editing system |
-
1981
- 1981-05-13 JP JP7163581A patent/JPS57186892A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6076890A (en) * | 1983-10-03 | 1985-05-01 | Nec Corp | Line concentration channel system |
JPS60143048A (en) * | 1983-12-29 | 1985-07-29 | Nec Corp | Line editing system |
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