JPS5637797A - Time-division multiple exchange system - Google Patents

Time-division multiple exchange system

Info

Publication number
JPS5637797A
JPS5637797A JP11344679A JP11344679A JPS5637797A JP S5637797 A JPS5637797 A JP S5637797A JP 11344679 A JP11344679 A JP 11344679A JP 11344679 A JP11344679 A JP 11344679A JP S5637797 A JPS5637797 A JP S5637797A
Authority
JP
Japan
Prior art keywords
supplied
different data
circuit
time
switchboard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11344679A
Other languages
Japanese (ja)
Other versions
JPS6239596B2 (en
Inventor
Masanori Oikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11344679A priority Critical patent/JPS5637797A/en
Publication of JPS5637797A publication Critical patent/JPS5637797A/en
Publication of JPS6239596B2 publication Critical patent/JPS6239596B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Abstract

PURPOSE:To reduce the processing load of the processor of the circuit connection, by carrying out a conversion so that the uniform emerging rate for the digital signals of different data speeds with each channel. CONSTITUTION:The data signal received a time-division multiplication and sent from each subscriber terminal 1 via the multiplexer 2 is supplied to each concentrating device 7 of the switchboard 4. At the device 7, the recomposition is given to secure the uniform emerging rate for the digital signals of different data speeds with each channel. Then the data signal is supplied to the exchange connecting circuit 8. The output of the circuit 8 is applied to the allotter device 9 to be converted again into the signals of different data speeds and then supplied to the terminal 14 each via the demultiplexer 13. In such way, the exchange connection can be processed in the form of the so-called unit traffic, and thus the processing load can be reduced greatly for the switchboard processor 5 of the circuit connection.
JP11344679A 1979-09-03 1979-09-03 Time-division multiple exchange system Granted JPS5637797A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11344679A JPS5637797A (en) 1979-09-03 1979-09-03 Time-division multiple exchange system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11344679A JPS5637797A (en) 1979-09-03 1979-09-03 Time-division multiple exchange system

Publications (2)

Publication Number Publication Date
JPS5637797A true JPS5637797A (en) 1981-04-11
JPS6239596B2 JPS6239596B2 (en) 1987-08-24

Family

ID=14612428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11344679A Granted JPS5637797A (en) 1979-09-03 1979-09-03 Time-division multiple exchange system

Country Status (1)

Country Link
JP (1) JPS5637797A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63305899A (en) * 1987-06-08 1988-12-13 株式会社　ヤハタ Mattress containing feather
JPH0389657U (en) * 1989-12-29 1991-09-12

Also Published As

Publication number Publication date
JPS6239596B2 (en) 1987-08-24

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