JPS60143048A - Line editing system - Google Patents

Abstract

PURPOSE:To attain miniaturization and to improve the operability by adopting a time division switch form to a local and a toll connecting system in a digital data line network so as to attain control memory control. CONSTITUTION:A time slot converting circuit is installed to an intraoffice line terminating section 9, plural intraoffice circuit terminating sections 9 are coupled on a multiplex bus 10 and controlled by line set information stored in control memory of a control section 14 so as to constitute a time division control switch. Thus, an optional line is accommodated in an optional time slot. Moreover, a local connection gate switch 13 ia provided on incoming/outgoing multiplex buses 10, 11 so as to generate a local line using an optional time slot.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a system for accommodating lines of a digital data network such as local lines and long-distance lines.

[Description of prior art]

In the digital data line network, data lines are divided into long-distance lines and local lines in order to accommodate and manage data lines. In the conventional system shown in Fig. 1, there is a station A and a station B, and data lines ZIZ2 and Zs-Ze are configured within the subscriber accommodation area of station A or B as a local line. Data lines 73 to 7 are transmitted between stations A and B via an inter-office transmission path between stations A and B.
4 is called a long-distance line.

Traditionally, in digital data networks, subscriber terminal speed data is stored at the customer subscriber terminal (DSU) in a so-called (6+2) envelope configuration (CCITT, X-5).
0) bearer signal. This bearer signal is then transmitted through the subscriber line and accommodated in the in-office equipment within the digital data line network.

The configuration of a conventional in-office device for this purpose is shown in FIG. This in-office equipment includes an in-office line termination unit (low-speed channel board) 1 that terminates the bearer signals transmitted through the subscriber line, and an inter-office line terminal unit that has the function of multiplexing the plurality of bearer signals and sending them out to the toll transmission line. Signal connections between the line termination unit (high-speed channel board) 2 and these multiple intra-office line termination units l and multiple inter-office line termination units 2 (long-distance line), or between multiple intra-office line termination units 1 Line editing terminal connection section (X-CONN) 3 and connection cable 4 for signal connection (local line)
(4-1, 4-2). The connection cable 4-1 is used for toll line connection, and the connection cable 4-2 is used for local line connection.

FIG. 3 shows the configuration of a conventional intra-office line termination section 1, which incorporates a subscriber line termination analog circuit 5 and a subscriber line termination digital circuit 6 connected in cascade. The configuration of the interoffice line termination section 2 is shown, in which a demultiplexing circuit 7 and an interoffice line termination circuit 8 are connected in cascade.

In the conventional system as described above, so-called line editing of local lines and long-distance lines is performed individually on a bearer signal basis using the connection cable 4 (4-1, 4 Therefore, in this method, the line editing terminal connection section 3 becomes physically very large, and the connection cable 4-1.
There were many problems in terms of comparison with 4-2, operability, reliability, etc.

[Purpose of the invention]

The present invention solves the above-mentioned conventional problems, and employs a time-division switch format for local and long-distance connections to reduce the size of the device, and employs control memory control to improve operability. The purpose of this invention is to provide a line editing method that can improve economy and reliability.

[Features of the invention]

The present invention provides a time slot conversion circuit composed of a memory having a speed conversion function in each of a plurality of channel boards that accommodate data signals, and converts each channel board into an uplink multiplexed bus and a downlink multiplexed bus. A gate switch for local connection is provided between the uplink multiplexed bus and the downlink multiplexed bus, and the write and read speeds and phases of the plurality of time slot conversion circuits or the gate for local connection are connected. A time slot generation circuit for controlling the switch, one common control memory for the uplink and downlink that stores the above line control information, a local line pair control circuit, and the local line that is the output thereof. A selection circuit that switches between control information and line control information output from the control memory when setting up a local line, and a decoder circuit that decodes this information and distributes it to the time slot conversion circuits in each channel board. A special feature characterized in that a control unit consisting of a controller centrally manages data signals accommodated in a channel board and converts them into required time slots 1- to set up long-distance lines and local lines. [Explanation based on an embodiment] FIG. 5 is a block diagram of a program of an embodiment of the line editing system of the present invention. control fa11 section 140 output 15 (15-1~l
An uplink multiplexed bus 10 and a downlink multiplexed bus 11 are provided on the output sides of the plurality of intra-office line termination units 9 to which 5-n) are respectively coupled, and an inter-office line termination unit 12 is provided on both north output sides. Connect. A local line connection gate consisting of an AND circuit 13a and an OR circuit 13b, into which the local line control pulse 26 of the control unit 14 is input, is located between the uplink multiplexed bus 10 and the downlink multiplexed bus 11. switch 1
3 to intervene.

FIG. 6 is a detailed block diagram of the intra-office line termination section 9 of the present invention. This time slot conversion circuit consists of a subscriber line termination analog circuit 16, a subscriber line termination digital circuit 17, and two time slot conversion circuits 18 connected in series.
“Channel pulses (C
) Is and CI R) 15 are input.

FIG. 7 is a detailed block diagram of the control section 14. As shown in FIG. The output of the time slot generation circuit 19 that manages the time slots and nodes of the line multiplexed buses 10 and 11 is the line editing information Ao that determines which intra-office line terminal bearer signal is accommodated in the time slot, and the line Local line?
It is coupled to a control memory 20 that stores line editing information Bo for determining whether it is a toll line. Constantly monitors the line editing information Ao ``Ao' output of the local line pair control circuit 21 that specifies the two intra-office line termination units 9 that form a pair in the case of the local line, and the line editing information 99 Bo; A local line control pulse 26 of the output signal of the local line control circuit 22 that determines whether the line is a local line, and if it is a local line, it is converted by the local line pair control circuit 21. Line editing information Ao' and line editing information QfJ A which is the output of the control memory 20 if it is a toll line.

are respectively input to the selection circuit 23. Its output is CI
l input to the decoder circuit 25 that generates the S pulse 15, and the decoder circuit 2 that also generates the C1l R pulse 15;
4 is output line editing information A of the control memory 20;

input directly.

The operation will be explained in detail below.

Now, the number of in-office line termination sections 9 accommodated is n, the number of time slots of multiplexed buses 10 and 11 is N, and one bearer line terminated at in-office line termination section 9 is installed in each time slot.
There shall be one correspondence. The time slot generation circuit 19 of the control section 14 sequentially generates the N time slots. and the above n1 for each time slot.
Line editing information Ao associates the line Il with line editing information Ao, and information as to whether or not it is a local line is stored as line editing information Bo in the control memory 20 as binary information. There are various control algorithms for the local line pair control circuit 21, but as an example, suppose the line numbers are m and m+1 (
However, if m is an odd number and m<n) is considered as a pair, information exchange from m to m+1 or information exchange from m+1 to m can be performed by performing complement conversion of the binary LSB bit. The information after this conversion is the line editing information Ao', and these pieces of information are converted into time slots by the decoder circuits 24 and 25 as CHS for uplink control and CHR pulse for downlink control in the in-office circuit termination unit 9. circuit 1
It is divided into 8. This time slot conversion circuit 18 is
A bearer signal from a subscriber is input, the speed is converted, and the bearer signal is periodically outputted to the uplink multiplex bus 10 in the phase of the C1 (S pulse).

Conversely, from the downlink multiplexed bus 11 to the CIl
The relevant bearer signal specified by the R pulse is periodically input to the time slot conversion circuit 18, speed-converted, and output to the subscriber side. , and line numbers x, i+ accommodated in time slot numbers I and K shown in FIG.
When the two lines No. 1 generate a local line, the local line control pulse 26 of the local line control circuit 22 operates the local connection gate switch 13 at time slot numbers I and K, and the uplink line A "crossover" (passage) is created between the multiplexed bus 10 for the downlink and the multiplexed bus 11 for the downlink, and the time slot control of the uplink and downlink pairs is performed as shown in FIG. A local line is generated as shown.

In the case of a toll line, the above-mentioned operation for local line connection is stopped and a toll line is generated using the same time slot for both uplink and downlink.

This will be explained in detail with reference to FIGS. 8 and 9.

FIG. 8 is an explanatory diagram including an operation time chart when accommodating local lines. The drawing symbols ■ and K indicate time slot numbers on the multiplexed bus, and information is written in the control memory 20 to accommodate the line number i+1 in the line number tsK, and the line editing information Ao is read. It's being served. Now, since i and i+l are a local line pair,
Line editing information Ao' is generated under the control of the local line pair control circuit 21. These line editing information Ao
, Ao' are decoded by decoder circuits 24 and 25 to generate 15-1 CH pulses and 15-(i+1) CH pulses. As is clear from this, in time slot ■, 15-i CIS pulse and 15-i CIS pulse
(i+1) CIl R pulses are generated, resulting in the 8th
The information of ■ in Figure 1b) is 15-1 to 15-(i+1)
transmitted to.

Similarly, in time slot K, the information ``■'' is 15-(
i+1) to 15-1, resulting in a full-duplex local line.

FIG. 9 is an explanatory diagram including an operation time chart 1- when accommodating a toll line. In this case, since it is a long-distance line, the contents of line editing information AO and Ao' are exactly the same, and the CIl S pulse and CI R pulse of 15-1 occur simultaneously in time slot ■, and 15-( i+1)
Similarly, the CHS pulse and the C) R pulse occur simultaneously in time slot K, resulting in the information shown in Figure 9(b).
0, ■, ■, ■, and mutually independent full-duplex toll lines are generated.

〔Effect of the invention〕

As described above, according to the present invention, with the basic configuration shown in FIG. (2) Uplink and downlink multiplexed bus that configures a time-division control switch and allows any line to be accommodated in any time slot by controlling the line setting information stored in the A gate switch for local connection is provided on the top, and a local line pair control circuit, local line control circuit, and selection circuit generate COS pulses for uplink control and CHR for downlink control from one line setting information.
(3) Compared to the conventional space division method, the connection method is made smaller by using a time division switch method, and operability is improved by control memory control. This has the effect of making it possible to improve economic efficiency and reliability.

[Brief explanation of the drawing]

Figure 2 is a schematic diagram showing the configuration of toll lines and local lines. Figure 2 is a diagram showing the conventional system configuration for long-distance lines and local lines. FIG. 3 is a detailed block diagram of the intra-office line termination section of FIG. 2. FIG. 4 is a detailed block diagram of the interoffice line termination section of FIG. 2. FIG. 5 is a block diagram of the system of the present invention for toll lines and local lines. FIG. 6 is a detailed block diagram of the intra-office line termination section of FIG. 5. FIG. 7 is a detailed block diagram of the control section of FIG. 6. FIG. 8 is an explanatory diagram including an operation time chart of the local line system of the present invention. FIG. 9 is an explanatory diagram including an operation time chart of the toll line system of the present invention. 1.9... Intra-station line termination section, 2.12... Inter-office line termination section, 3... Line editing terminal connection section, 4... Connection cable, 5.16... Subscriber line Analog circuit for termination, 6.17...Digital circuit for subscriber line termination, 7.
・・Demultiplexing circuit, 8 ・・Inter-office line termination circuit, 10
... Multiplexed bus for uplink, 11... Multiplexed bus for downlink, 13... Gate switch for city connection, 14
...Control unit, 18...Time slot conversion circuit, 1
9... Time slot generation circuit, 20... Control memory, 21... Local line pair control circuit, 22...
・City line control circuit, edict... selection circuit, 24, b...
・Decoder, I, K...Time slot number. Patent applicant agent Patent attorney Ide Nao Takashi Z3 Z4 1st mouth M 2 ro 3rd son M 4 times 5 mouths 7 Diagram 9 Figure 1, Yuyo □yo

Claims (1)

[Claims] (1) In a line editing system that includes an intra-office line termination section, an inter-office line termination section, and a line editing terminal connection section connected between the two line ends, the above-mentioned intra-office line termination section is equipped with a speed converter. The line editing terminal connection section includes an uplink multiplexed bus and a downlink multiplexed bus to which the intra-office line termination section is connected, and the uplink multiplexed bus. a gate switch for local connection interposed between the multiplexed bus for the downlink and the multiplexed bus for the downlink; Furthermore, there is a time slot generation circuit that controls the gate switch for local connections, a control memory common to the uplink and downlink that stores the line control information, a local line pair control circuit, and the output of this circuit. a selection circuit that switches between the local circuit control information, which is , and the line control information, which is the output of the control memory, when setting the local circuit, and a selection circuit that decodes each of the above information,
It includes a decoder circuit that distributes the data signals corresponding to the time slot conversion circuits in each intra-office circuit termination section, and this control section centrally manages each of the above circuits and converts the data signals accommodated in the intra-office circuit termination section into the required data signals. A line editing method characterized by being configured to convert to time slots and set long distance lines and local lines.