JPH0618356B2 - Multiple conversion circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex conversion circuit for a digital synchronous terminal station in a digital synchronous network.

(Prior Art) A digital synchronous terminal system in a digital synchronous network is
For example, "Facility" Vol. 34 No. 1 (January 15, 1982)
Japan) Telecommunications Association, "City suburbs digital synchronization terminal system <3>", P. 99-P. As described in 112, by synchronizing the digital primary group (1.544 Mbit / s) and the digital secondary group (6.312 Mbit / s) and making the frame structure into an octet multiplex format, a digital exchange, etc. 8.192 Mbit / s or 2.0 between various signal sources
It is connected via a 48 Mbit / s in-station interface.

One of the basic functions of the digital synchronous terminal equipment in the digital synchronous network is 1.544 Mbit / s.
Digital primary group interface or 6.312 Mbi
Transmission line interface such as t / s digital secondary group interface, 8.192 Mbit / s or 2.048 Mbit / s
There is a multiplex conversion function that performs multiplex conversion between the intra-station interfaces.

1.544Mbit / s digital primary group, 6.312Mbit
The transmission capacity of each transmission line interface of the / s digital secondary group is 24 channels and 96 channels in terms of 64 Kbit / s telephone channel, respectively, and 2.048
The transmission capacity of each intra-station interface of Mbit / s and 8.192 Mbit / s is 30 channels and 120 channels, respectively. Due to the difference in the transmission rate and the channel capacity in each of these interfaces, a multiplex conversion function for converting between these interfaces is often required in the digital synchronization terminal station.

As another example in which a multiple conversion function is required, PCM
This is a multiple conversion function in the multiple conversion device. As for the PCM multiplex conversion device, as shown in the above-mentioned document, the area 2 type
24 channels (1.578 in the PCM multiplex converter)
Mbit / s) x 496 channels (6.312 Mbit / s),
24 channels (2.048 Mbit / s) x 5120 channels (8.1
92 Mbit / s), and 24 channels (2.048 Mbit / s) x 530 in the local 3B type PCM multiplexer.
Various multiple conversion functions such as channel (2.048 Mbit / s) × 4 are required.

(Problems to be Solved by the Invention) In the digital synchronization terminal station system, not only the representative example described above but also connections between interfaces, connections between digital synchronization multi-order groups, and between digital synchronization terminals are further developed. It is considered that various multiple conversions are required to meet various demands such as connection.

Conventionally, the hardware that realizes such a multiplex conversion function is generally configured to individually correspond to various conditions of the input / output interface such as the channel capacity of the input / output interface, the signal speed, the signal multiplexing format, and the number of highways. Therefore, it has a drawback that the hardware is completely restricted by the individual conditions of the input / output interface.

(Means for Solving the Problems) The present invention inputs five highway input signals in parallel at 24 kbit / s at 64 kbit / s at a signal rate of 2.048 Mbit / s in parallel and outputs 120 channels in series. A parallel-serial conversion circuit for converting into a multiple signal, an address counter for generating a write address signal, an address conversion memory for converting a write address generated by the address counter into a read address signal, and a write address signal for the address counter. By the series
1. A 120-channel multiplexed signal is temporarily stored, and a data memory for serially reading the temporarily stored data for each channel by a read address signal of the address conversion memory, and a serial 120-channel multiplexed signal read from the data memory A serial-parallel conversion circuit for converting four parallel highway data multiplexed at 30 channels at 64 kbit / s at a signal rate of 048 Mbit / s, and time slot conversion from the data memory by the read address signal. Then, the channel is serially read for each channel, and the serial-parallel conversion circuit sequentially allocates the read serial data in order of four highways to form parallel data.

(Operation) The multiplex conversion circuit of the present invention includes a parallel-serial conversion circuit, an address counter, an address conversion memory, a data memory, and a serial-parallel conversion circuit.

The data memory temporarily stores the serial channel multiplexed signal obtained by converting the parallel highway input signal by the parallel-serial conversion circuit, converts the temporarily stored signal into a time slot, and reads the serially for each channel to perform the serial-parallel conversion circuit. Send to. The serial-parallel conversion circuit sequentially assigns the read serial signals in a predetermined highway order to form parallel signals.
Then, the temporary storage of the serial channel multiplexed signal in the data memory is performed according to the write address signal generated by the address counter, and the temporarily stored signal is serially read for each channel by changing the write address signal of the address counter to the address. This is performed according to the read address signal converted by the conversion memory.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which an input terminal IN is connected to an input of a parallel-series conversion circuit 1 and a parallel-
The output of the serial conversion circuit 1 is connected to the data input of the data memory 2, the output of the data memory 2 is connected to the input of the serial-parallel conversion circuit 5, and the output of the serial-parallel conversion circuit 4 is connected to the output terminal OUT. The output of the address counter 3 is connected to the address input of the data memory 2 and the address input of the address conversion memory, and the output of the address conversion memory 4 is connected to the address input of the data memory 2.

This multiplex conversion circuit can be used for 24 channels (2.048 Mbit / s) × 5 → 30 in the 3B type PCM multiplex conversion device in the toll system.
Channel (2.048 Mbit / s) x 4 multiplex conversion (5
This is called / 4 conversion. ) Will be described.

FIG. 2 is a time chart showing the conversion process of the 5/4 conversion. In FIG. 2, the input terminal IN of FIG.
Is the input signal of the multiplex conversion circuit given to. The input signal has a signal rate of 2.048 Mbit / s and the channel multiplexing format is 24 in the distributed arrangement as shown in FIG.
Channel signals are octet-multiplexed (multiplexing method in which 8 bits corresponding to one sample value of each channel are collectively collected)
Has been done. Five such 24-channel multiplexed signals, that is, five highways (HW), are applied to the input terminal IN. Further, in FIG. 2, is the output signal of the multiplex conversion circuit to be sent to the output terminal OUT of FIG. The output signal also has a signal rate of 2.048 Mbit / s, and the channel multiplexing format is a octet-multiplexed signal of 30 channels in a distributed arrangement as shown in FIG. Such a 30-channel multiplexed signal is sent to the output terminal OUT on four highways.

The parallel-serial conversion circuit 1 bit-multiplexes a 24-channel multiplexed signal of 5 highways to form a 120-channel multiplexed signal (FIG. 2), expands this signal in octets (8 bits) in parallel for each channel, and Converted to octet parallel 120-channel multiplexed signal. The octet parallel 120-channel multiplexed signal converted by the parallel-serial conversion circuit 1 is written in the data memory 2. The write address of the data memory 2 is given by the write address signal generated by the address counter 3. On the other hand, the write address signal generated by the address counter 3 is converted into a read address by the address conversion memory 4,
This read address is given to the address input of the data memory 2. The address translation memory 4 is composed of, for example, a ROM (read-only memory), receives a write address, and generates a read address corresponding to the write program. It should be noted that by using an EPROM as the ROM, versatility can be provided. The 120-channel multiplexed signal stored in the data memory 2 is subjected to tie slot conversion in the order designated by the read address generated by the address conversion memory 4 and read.

Octet parallel 120 read from data memory 2
Channel-multiplexed signals are sequentially output by the serial-parallel conversion circuit 5 to 4
Assigned in the order of highways, converted into 30-channel multiplexed signals of 4-octet octet multiplexing format and output terminals
It is sent to OUT.

The 5 highway 24 channel multiplexed signal thus input is converted into a 4 highway 30 channel multiplexed signal. The conversion content of this multiple conversion depends on the program of the address conversion memory as described above.

(Effects of the Invention) According to the present invention, it is possible to realize a versatile multiplex conversion circuit by unified hardware without being restricted by individual conditions of the input / output interface.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
It is a flowchart of a figure. 1 ... Parallel-serial conversion circuit, 2 ... Data memory, 3 ...
... Address counter, 4 ... Address translation memory, 5 ...
... serial-parallel conversion circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Noriyuki Terada Inventor Noriyuki 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Public Corporation (56) References JP-A-56-109091

Claims (1)

[Claims] 1. A high-speed input signal having a signal speed of 2.048 Mbit / s, which is multiplexed with 24 channels at 64 kbit / s for 24 channels, is input in parallel, and 120 in series.
A parallel-serial conversion circuit for converting into a channel multiplexed signal, an address counter for generating a write address signal, an address conversion memory for converting a write address generated by the address counter into a read address signal, and a write address of the address counter A data memory for temporarily storing the serial 120-channel multiplexed signal by a signal, and serially reading the temporarily stored data for each channel by a read address signal of the address conversion memory; and a serial 120 channel read from the data memory. 4 multiplexed 30 signals at 64 kbit / s per channel at a signal rate of 2.048 Mbit / s
Serial-parallel conversion circuit for converting into one parallel highway data, and time-slot conversion is performed from the data memory by the read address signal to read serially for each channel, and the serial-parallel conversion circuit reads the data. The serial conversion data is sequentially assigned in the order of four highways to form parallel data, which is a multiplex conversion circuit.