JPS57186356A - Semiconductor memory storage - Google Patents

Semiconductor memory storage

Info

Publication number
JPS57186356A
JPS57186356A JP7093981A JP7093981A JPS57186356A JP S57186356 A JPS57186356 A JP S57186356A JP 7093981 A JP7093981 A JP 7093981A JP 7093981 A JP7093981 A JP 7093981A JP S57186356 A JPS57186356 A JP S57186356A
Authority
JP
Japan
Prior art keywords
written
amorphous
wiring
resistance
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7093981A
Other languages
Japanese (ja)
Other versions
JPH0332228B2 (en
Inventor
Seiichi Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP7093981A priority Critical patent/JPS57186356A/en
Publication of JPS57186356A publication Critical patent/JPS57186356A/en
Publication of JPH0332228B2 publication Critical patent/JPH0332228B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain a read-only memory, which has high reliability and can be written electrically, through a conduction type writing system by disusing fussion type writing. CONSTITUTION:Doped poly Si 13 is formed onto the SiO2 film 12 of an Si substrate 11. Ar ions are injected and amorphous Si 14 is shaped partially, the whole is temporarily changed into a bad conductor, the surface is coated with CVD SiO2 15, and Al wiring 16 is attached. When the layer 14 is conducted and annealed, its resistance lowers, and the amorphous Si does not become reversible reverse bias. Accordingly, information of which an initial high-resistance consition is made ''0'' and a low resistance condition after electric annealing ''1'' can be written. The information can be written electrically with high reliability because there happens no incomplete fusing and short circuit of wiring at that time.
JP7093981A 1981-05-12 1981-05-12 Semiconductor memory storage Granted JPS57186356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7093981A JPS57186356A (en) 1981-05-12 1981-05-12 Semiconductor memory storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7093981A JPS57186356A (en) 1981-05-12 1981-05-12 Semiconductor memory storage

Publications (2)

Publication Number Publication Date
JPS57186356A true JPS57186356A (en) 1982-11-16
JPH0332228B2 JPH0332228B2 (en) 1991-05-10

Family

ID=13445967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7093981A Granted JPS57186356A (en) 1981-05-12 1981-05-12 Semiconductor memory storage

Country Status (1)

Country Link
JP (1) JPS57186356A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62188243A (en) * 1985-10-18 1987-08-17 レヴイ　ガ−ズバ−グ Method and structure for connecting electric circuit elements selectively
WO1992007380A1 (en) * 1990-10-15 1992-04-30 Seiko Epson Corporation Semiconductor device having switching circuit to be switched by light and its fabrication process
EP1320131A3 (en) * 2001-11-20 2004-12-01 Zarlink Semiconductor Limited antifuses
JP2007230643A (en) * 2006-03-03 2007-09-13 Dainippon Printing Co Ltd Cup-shaped container with non-contact ic tag

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061730U (en) * 1973-10-09 1975-06-06

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061730U (en) * 1973-10-09 1975-06-06

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62188243A (en) * 1985-10-18 1987-08-17 レヴイ　ガ−ズバ−グ Method and structure for connecting electric circuit elements selectively
WO1992007380A1 (en) * 1990-10-15 1992-04-30 Seiko Epson Corporation Semiconductor device having switching circuit to be switched by light and its fabrication process
EP1320131A3 (en) * 2001-11-20 2004-12-01 Zarlink Semiconductor Limited antifuses
JP2007230643A (en) * 2006-03-03 2007-09-13 Dainippon Printing Co Ltd Cup-shaped container with non-contact ic tag

Also Published As

Publication number Publication date
JPH0332228B2 (en) 1991-05-10

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