JPS57183159A - Digital transmission system - Google Patents
Digital transmission systemInfo
- Publication number
- JPS57183159A JPS57183159A JP56067977A JP6797781A JPS57183159A JP S57183159 A JPS57183159 A JP S57183159A JP 56067977 A JP56067977 A JP 56067977A JP 6797781 A JP6797781 A JP 6797781A JP S57183159 A JPS57183159 A JP S57183159A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- terminal
- flop
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4902—Pulse width modulation; Pulse position modulation
Landscapes
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To facilitate the digital IC-implementation of a receiver for a signal modulated into the long-short data of the transition time of a synchronizing signal by an information, by composing the receiver of a threshold value circuit, a delay circuit, and a flip-flop. CONSTITUTION:A long-short data code is applied to the input terminal 1 of a transmitting circuit 6 and then inputted to an output circuit 3. A clock signal applied to a terminal 2 is applied to the anode of a varactor diode 5. The varactor diode 5 when biased reversely increases in junction capacity, and at the output terminal 4 of the transmitting circuit 6, a signal generated by varying the transition time of the clock signal according to the long-short data code to the input terminal 1 appears. At a reception side, the signal is inputted to an edge trigger type flip-flop 18 having a threshold level VT1 (>VT2) and also inputted to an edge trigger type flip-flop 18 through a threshold circuit 13 having a threshold value VT2 and a delay circuit 15, regenerating an original signal at a terminal 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56067977A JPS57183159A (en) | 1981-05-06 | 1981-05-06 | Digital transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56067977A JPS57183159A (en) | 1981-05-06 | 1981-05-06 | Digital transmission system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57183159A true JPS57183159A (en) | 1982-11-11 |
Family
ID=13360550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56067977A Pending JPS57183159A (en) | 1981-05-06 | 1981-05-06 | Digital transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57183159A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100656102B1 (en) * | 1996-11-27 | 2007-05-14 | 소니 유나이티드 킹덤 리미티드 | One-bit digital signal processing |
-
1981
- 1981-05-06 JP JP56067977A patent/JPS57183159A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100656102B1 (en) * | 1996-11-27 | 2007-05-14 | 소니 유나이티드 킹덤 리미티드 | One-bit digital signal processing |
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