JPS57174757A - Multi-microcomputer system - Google Patents
Multi-microcomputer systemInfo
- Publication number
- JPS57174757A JPS57174757A JP56060823A JP6082381A JPS57174757A JP S57174757 A JPS57174757 A JP S57174757A JP 56060823 A JP56060823 A JP 56060823A JP 6082381 A JP6082381 A JP 6082381A JP S57174757 A JPS57174757 A JP S57174757A
- Authority
- JP
- Japan
- Prior art keywords
- lmc
- power supply
- microcomputer
- mmc
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To increase both the operability and the practical application of a multi-microcomputer system, by giving the ON control to the power supply of a local microcomputer via a main microcomputer and at the same time securing the mutual confirmation for the CPU breakdown state, etc. between the above- mentioned two computers. CONSTITUTION:A main microcomputer MMC turns on the power supply of a local microcomputer LMC. For this purpose, a CPU1 stores the power supply ON data of the computer LMC in a general register GR1 and delivers it to a latch buffer register LBR12 through a terminal O14. This data is then supplied to a driver RYD via FLC12 and FLC21, and the power supply PO of the computer LMC is turned on a relay RY. Both computers MMC and LMC exchange the CPU breakdown information or the fault state information to each other. In this case, for instance, the computer MMC delivers the watchdog signal WD1 which shows a fault state like a program error, etc. to the FLC12 from a terminal O10 via a gate OR1 along with the gate CPU breakdown signal CD1 delivered through a terminal O11.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56060823A JPS57174757A (en) | 1981-04-22 | 1981-04-22 | Multi-microcomputer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56060823A JPS57174757A (en) | 1981-04-22 | 1981-04-22 | Multi-microcomputer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57174757A true JPS57174757A (en) | 1982-10-27 |
Family
ID=13153455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56060823A Pending JPS57174757A (en) | 1981-04-22 | 1981-04-22 | Multi-microcomputer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57174757A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102593866A (en) * | 2012-02-23 | 2012-07-18 | 中电普瑞科技有限公司 | Unified power flow controller based on modular multilevel converter structure |
-
1981
- 1981-04-22 JP JP56060823A patent/JPS57174757A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102593866A (en) * | 2012-02-23 | 2012-07-18 | 中电普瑞科技有限公司 | Unified power flow controller based on modular multilevel converter structure |
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