JPS57171859A - Code error detecting system - Google Patents

Abstract

PURPOSE:To reduce the operating speed required by the counter to a half of the transmitting speed, to minimize the scale of the circuit, and to sufficiently cope with high transmitting speed, by judging error detections with a pulse whose cycle is half as much as that of the clock. CONSTITUTION:By inputting 5B6B codes into an input terminal 37 and a clock pulse into a clock pulse input terminal 38, the output of a D type FF13 is supplied to a 2-bit adder 34 and, at the same time, the clock pulse is added to the adder 34. Additions of every 2 bits of the code sequence are performed by the adder 34 and outputs (f) and (g) obtained as the result of the additions are inputted into an RDS counter 35. The counter 35 supervises three conditions of the outputs (f) and (g) and, when the result of the additions exceeds the upper limit or the lower limit of a prescribed range, alternately outputs +(plus) error or - (minus) error. The output from the counter 35 is inputted into a removing circuit 36 which removes the + error and - error, and the + error and - error alternately produced are removed, and thus, errors are removed corresponding to the high transmitting speed.