JPS57168564A - Channel memory checking system - Google Patents

Channel memory checking system

Info

Publication number
JPS57168564A
JPS57168564A JP5239181A JP5239181A JPS57168564A JP S57168564 A JPS57168564 A JP S57168564A JP 5239181 A JP5239181 A JP 5239181A JP 5239181 A JP5239181 A JP 5239181A JP S57168564 A JPS57168564 A JP S57168564A
Authority
JP
Japan
Prior art keywords
channel
memory
data
fault
call
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5239181A
Other languages
English (en)
Japanese (ja)
Other versions
JPS641990B2 (enrdf_load_html_response
Inventor
Hiyoshi Goto
Jutaro Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Taiko Electric Works Ltd
Original Assignee
Oki Electric Industry Co Ltd
Taiko Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd, Taiko Electric Works Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5239181A priority Critical patent/JPS57168564A/ja
Publication of JPS57168564A publication Critical patent/JPS57168564A/ja
Publication of JPS641990B2 publication Critical patent/JPS641990B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H04M3/244—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Exchange Systems With Centralized Control (AREA)
JP5239181A 1981-04-09 1981-04-09 Channel memory checking system Granted JPS57168564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5239181A JPS57168564A (en) 1981-04-09 1981-04-09 Channel memory checking system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5239181A JPS57168564A (en) 1981-04-09 1981-04-09 Channel memory checking system

Publications (2)

Publication Number Publication Date
JPS57168564A true JPS57168564A (en) 1982-10-16
JPS641990B2 JPS641990B2 (enrdf_load_html_response) 1989-01-13

Family

ID=12913498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5239181A Granted JPS57168564A (en) 1981-04-09 1981-04-09 Channel memory checking system

Country Status (1)

Country Link
JP (1) JPS57168564A (enrdf_load_html_response)

Also Published As

Publication number Publication date
JPS641990B2 (enrdf_load_html_response) 1989-01-13

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