JPS57166590A - Generator for day-off signal - Google Patents
Generator for day-off signalInfo
- Publication number
- JPS57166590A JPS57166590A JP56052609A JP5260981A JPS57166590A JP S57166590 A JPS57166590 A JP S57166590A JP 56052609 A JP56052609 A JP 56052609A JP 5260981 A JP5260981 A JP 5260981A JP S57166590 A JPS57166590 A JP S57166590A
- Authority
- JP
- Japan
- Prior art keywords
- day
- output
- gate
- mode
- setting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G15/00—Time-pieces comprising means to be operated at preselected times or after preselected time intervals
- G04G15/003—Time-pieces comprising means to be operated at preselected times or after preselected time intervals acting only at one preselected time or during one adjustable time interval
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electric Clocks (AREA)
Abstract
PURPOSE:To prevent unnecessary power consumption by a load by detecting the day before a day off automatically and then switching an automatic controller for the load to a day-off mode automatically after a store is closed on the day before the day off. CONSTITUTION:One day-off setting switch corresponds to a day off among day-off setting swithes 4-1, 4-2-4-7 is turned off previously. In a time setter 13, closing time is set in advance. At twelve o'clock midnight on the day before the day off, a shift register 3 which generates a signal showing a day of the week one day earlier than normal generates an output and the output of an OR gate 6-2 goes up to a 1. At the closing time, a comparator 12 outputs a 1, so an AND gate 11 outputs a 1, thereby switching an automatic controller to a day-off mode through a terminal 10. On the actual day off, the output of a register 1 for the normal calender inverts the output of an OR gate 8 to a 1, thus setting the day-off mode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56052609A JPS57166590A (en) | 1981-04-07 | 1981-04-07 | Generator for day-off signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56052609A JPS57166590A (en) | 1981-04-07 | 1981-04-07 | Generator for day-off signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57166590A true JPS57166590A (en) | 1982-10-14 |
Family
ID=12919532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56052609A Pending JPS57166590A (en) | 1981-04-07 | 1981-04-07 | Generator for day-off signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57166590A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5244555A (en) * | 1975-10-06 | 1977-04-07 | Ise Electronics Corp | Timer equipment |
-
1981
- 1981-04-07 JP JP56052609A patent/JPS57166590A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5244555A (en) * | 1975-10-06 | 1977-04-07 | Ise Electronics Corp | Timer equipment |
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