JPS57162071A - Vector arithmetic processor - Google Patents

Vector arithmetic processor

Info

Publication number
JPS57162071A
JPS57162071A JP4753281A JP4753281A JPS57162071A JP S57162071 A JPS57162071 A JP S57162071A JP 4753281 A JP4753281 A JP 4753281A JP 4753281 A JP4753281 A JP 4753281A JP S57162071 A JPS57162071 A JP S57162071A
Authority
JP
Japan
Prior art keywords
data
double structure
register
arithmetic processor
vector arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4753281A
Other languages
Japanese (ja)
Inventor
Hiroshi Murayama
Hitoshi Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4753281A priority Critical patent/JPS57162071A/en
Publication of JPS57162071A publication Critical patent/JPS57162071A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To perform the simultaneous writing for the data registers which are in the reading mode, by securing a double structure for the data register and using alternately each block. CONSTITUTION:A data register DR2 has a double structure like R00 and R01, R10 and R11 plus R20 and R22 respectively. The vector data read out of a main storage device MS1 is once stored in the register DR2 and then calculated by an operator 3. The result of this operation is stored again in the DR2 to be finally stored in the device MS1. As the DR2 has a double structure and each block is used alternately, the next data can be written into the R01 simultaneously with the data of the R00 which are being read for example. In such way, the simultaneous writing is possible to the data register which is in the reading mode.
JP4753281A 1981-03-31 1981-03-31 Vector arithmetic processor Pending JPS57162071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4753281A JPS57162071A (en) 1981-03-31 1981-03-31 Vector arithmetic processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4753281A JPS57162071A (en) 1981-03-31 1981-03-31 Vector arithmetic processor

Publications (1)

Publication Number Publication Date
JPS57162071A true JPS57162071A (en) 1982-10-05

Family

ID=12777730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4753281A Pending JPS57162071A (en) 1981-03-31 1981-03-31 Vector arithmetic processor

Country Status (1)

Country Link
JP (1) JPS57162071A (en)

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