JPS57162011A - Sense byte holding system - Google Patents
Sense byte holding systemInfo
- Publication number
- JPS57162011A JPS57162011A JP56047425A JP4742581A JPS57162011A JP S57162011 A JPS57162011 A JP S57162011A JP 56047425 A JP56047425 A JP 56047425A JP 4742581 A JP4742581 A JP 4742581A JP S57162011 A JPS57162011 A JP S57162011A
- Authority
- JP
- Japan
- Prior art keywords
- input
- controller
- output
- ioc1
- cpu1
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To elevate reliability of a system and its throughput, by holding discriminating information of the system and its sense byte by an input/output device, and designating and sending out the discriminating information of its sense byte, in a sense byte holding system of a magnetic disk subsystem. CONSTITUTION:A CPU1 issued an input/output instruction to an input/output device I01 through a route of a channel CH1, and an input/output controller IOC1. Subsequently, system discriminating information ID for informing that the input/output operation has been started by the instruction of the CPU1 is held by the device I01. When a fault occurs in the course of this operation, the controller IOC1 generates a sense byte to the device IO1, and also informs a unit check to the CPU1. The CPU1 which has received this report issues a sense instruction together with the information ID of the CPU to a route E having the same information ID as a route A, in case when the controller IOC1 is busy and the route A cannot be utlized. An input/output controller IOC2 which has received this instruction reads the sense byte from the controller IOC1 and reports it to a channel 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56047425A JPS57162011A (en) | 1981-03-31 | 1981-03-31 | Sense byte holding system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56047425A JPS57162011A (en) | 1981-03-31 | 1981-03-31 | Sense byte holding system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57162011A true JPS57162011A (en) | 1982-10-05 |
Family
ID=12774794
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56047425A Pending JPS57162011A (en) | 1981-03-31 | 1981-03-31 | Sense byte holding system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57162011A (en) |
-
1981
- 1981-03-31 JP JP56047425A patent/JPS57162011A/en active Pending
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