JPS57157623A - Pulse width extending circuit - Google Patents

Pulse width extending circuit

Info

Publication number
JPS57157623A
JPS57157623A JP4207581A JP4207581A JPS57157623A JP S57157623 A JPS57157623 A JP S57157623A JP 4207581 A JP4207581 A JP 4207581A JP 4207581 A JP4207581 A JP 4207581A JP S57157623 A JPS57157623 A JP S57157623A
Authority
JP
Japan
Prior art keywords
circuit
output
voltage
impressed
logical operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4207581A
Other languages
Japanese (ja)
Other versions
JPH0123006B2 (en
Inventor
Koichi Yomogihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Signal Co Ltd
Original Assignee
Nippon Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority to JP4207581A priority Critical patent/JPS57157623A/en
Publication of JPS57157623A publication Critical patent/JPS57157623A/en
Publication of JPH0123006B2 publication Critical patent/JPH0123006B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Pulse Circuits (AREA)

Abstract

PURPOSE:To realize a fail safe pulse width extending circuit, by installing an asymmetrical error delay circuit which does not generate any output pulses under some circuit troubles. CONSTITUTION:When no voltage is impressed upon an input terminal 1, an asymmetrical error logical operation circuit 6 of a storing circuit 5 stops its oscillation through an input line (a), and no voltage is impressed upon an output terminal 4. When a voltage is impressed upon an input pulse, the output of a differentiating circuit C1 is clamped by a hot side supply voltage +V0. An output line (c) becomes no-voltage condition after a time which is decided by the time constant of the differentiating circuit C1, after the asymmetrical error logical operation circuit 4 starts oscillating action and the output becomes a negative DC output -V. The output of another differentiating curcuit C2 is clamped by the hot side supply voltage +V0 at the rear edge of the output pulse of the output line (c), the asymmetrical error logical operation circuit makes oscillating action, and a voltage is impressed upon another output terminal 3. Therefore, even when a clamp diode D1 or D2 is in short-circuiting trouble and one differentiating circuit C1 or C2 makes a short-circuit, the asymmetrical error logical operation circuit 4 or 6 does not make any oscillating action and fail safe condition is realized.
JP4207581A 1981-03-23 1981-03-23 Pulse width extending circuit Granted JPS57157623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4207581A JPS57157623A (en) 1981-03-23 1981-03-23 Pulse width extending circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4207581A JPS57157623A (en) 1981-03-23 1981-03-23 Pulse width extending circuit

Publications (2)

Publication Number Publication Date
JPS57157623A true JPS57157623A (en) 1982-09-29
JPH0123006B2 JPH0123006B2 (en) 1989-04-28

Family

ID=12625935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4207581A Granted JPS57157623A (en) 1981-03-23 1981-03-23 Pulse width extending circuit

Country Status (1)

Country Link
JP (1) JPS57157623A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568131A (en) * 1993-03-31 1996-10-22 The Nippon Signal Co., Ltd. Motor rotation judgement circuit and apparatus using such circuit for verifying that a motor is stopped
US6657762B2 (en) 2000-01-06 2003-12-02 The Nippon Signal Co., Ltd. Optical barrier device
CN110065458A (en) * 2018-01-22 2019-07-30 罗伯特·博世有限公司 As the reaction to activation signal by the method for circuit device activation computing unit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023496A1 (en) * 1993-03-31 1994-10-13 The Nippon Signal Co., Ltd. On-delay circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4844457U (en) * 1971-09-30 1973-06-09
JPS4952960A (en) * 1972-09-25 1974-05-23
JPS5516501A (en) * 1978-06-14 1980-02-05 Nippon Signal Co Ltd:The Fail-safe logic circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4844457U (en) * 1971-09-30 1973-06-09
JPS4952960A (en) * 1972-09-25 1974-05-23
JPS5516501A (en) * 1978-06-14 1980-02-05 Nippon Signal Co Ltd:The Fail-safe logic circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568131A (en) * 1993-03-31 1996-10-22 The Nippon Signal Co., Ltd. Motor rotation judgement circuit and apparatus using such circuit for verifying that a motor is stopped
US6657762B2 (en) 2000-01-06 2003-12-02 The Nippon Signal Co., Ltd. Optical barrier device
CN110065458A (en) * 2018-01-22 2019-07-30 罗伯特·博世有限公司 As the reaction to activation signal by the method for circuit device activation computing unit
KR20190089741A (en) * 2018-01-22 2019-07-31 로베르트 보쉬 게엠베하 Method for activating a computer unit by a circuit device in response to an activation signal

Also Published As

Publication number Publication date
JPH0123006B2 (en) 1989-04-28

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