KR960008422B1 - Apparatus for duplexing hot stand-by controlling circuit - Google Patents

Apparatus for duplexing hot stand-by controlling circuit Download PDF

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Publication number
KR960008422B1
KR960008422B1 KR93016860A KR930016860A KR960008422B1 KR 960008422 B1 KR960008422 B1 KR 960008422B1 KR 93016860 A KR93016860 A KR 93016860A KR 930016860 A KR930016860 A KR 930016860A KR 960008422 B1 KR960008422 B1 KR 960008422B1
Authority
KR
South Korea
Prior art keywords
flip flop
output
gate
receives
duplexing
Prior art date
Application number
KR93016860A
Other languages
Korean (ko)
Other versions
KR950007579A (en
Inventor
Bae-Hyung Kim
Original Assignee
Daewoo Telecom Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daewoo Telecom Co Ltd filed Critical Daewoo Telecom Co Ltd
Priority to KR93016860A priority Critical patent/KR960008422B1/en
Publication of KR950007579A publication Critical patent/KR950007579A/en
Application granted granted Critical
Publication of KR960008422B1 publication Critical patent/KR960008422B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • H04Q1/30—Signalling arrangements; Manipulation of signalling currents

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

a first flip flop (24) which has falling edge signal as the input; a second flip flop (21) which has falling edge signal as the input; a third flip flop (22) which inputs the positive output (Q) of the second flip flop (21); a first NAND gate (31) which supplies the NAND result of positive output (Q) of the second flip flop (21) and the negative output (Q bar) of the third flip flop (22) to CLK of the first flip flop (24) as trigger pulse; a forth flip flop (23) which inputs the output of the NAND gate (31) and delays it; a voltage comparator (25); an inverter (26) which receives FFo; a first AND gate (27) which receives the output of the voltage comparator and the inverter; a second NAND gate (30) which receives the output of the first AND gate and the forth flip flop; an OR gate (29) which receives the output of the second NAND gate and the positive output (Q) of the opposite first flip flop (24); a second AND gate (28) which receives the output of the OR gate (29) and the output voltage (Vcc).
KR93016860A 1993-08-27 1993-08-27 Apparatus for duplexing hot stand-by controlling circuit KR960008422B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93016860A KR960008422B1 (en) 1993-08-27 1993-08-27 Apparatus for duplexing hot stand-by controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93016860A KR960008422B1 (en) 1993-08-27 1993-08-27 Apparatus for duplexing hot stand-by controlling circuit

Publications (2)

Publication Number Publication Date
KR950007579A KR950007579A (en) 1995-03-21
KR960008422B1 true KR960008422B1 (en) 1996-06-26

Family

ID=19362153

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93016860A KR960008422B1 (en) 1993-08-27 1993-08-27 Apparatus for duplexing hot stand-by controlling circuit

Country Status (1)

Country Link
KR (1) KR960008422B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498906B1 (en) * 1997-12-29 2005-09-16 삼성전자주식회사 Stable switching control circuit between redundant modules using side information

Also Published As

Publication number Publication date
KR950007579A (en) 1995-03-21

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