JPS5715538A - Automatic equalizing system for line delay distortion - Google Patents

Automatic equalizing system for line delay distortion

Info

Publication number
JPS5715538A
JPS5715538A JP8981880A JP8981880A JPS5715538A JP S5715538 A JPS5715538 A JP S5715538A JP 8981880 A JP8981880 A JP 8981880A JP 8981880 A JP8981880 A JP 8981880A JP S5715538 A JPS5715538 A JP S5715538A
Authority
JP
Japan
Prior art keywords
circuit
delay distortion
signal
frequency
receiving end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8981880A
Other languages
Japanese (ja)
Inventor
Susumu Sekiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8981880A priority Critical patent/JPS5715538A/en
Publication of JPS5715538A publication Critical patent/JPS5715538A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/14—Control of transmission; Equalising characterised by the equalising network used
    • H04B3/146—Control of transmission; Equalising characterised by the equalising network used using phase-frequency equalisers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To equalize the delay distortion of an information transmitting line automatically, by measuring the delay distortion at the receiving end and controlling the number of insertions of a delay equalizer inserted to the receiving end through the measuring value. CONSTITUTION:A signal having almost the center frequency in the transmission band for information transmission is outputted from a frequency oscillating circuit 1 and branched at a distribution circuit 2. One signal is taken as a signal having the frequency in the band different from the center frequency via a waveform converting circuit 3, a multiplying circuit 4 and a waveform circuit 5, it is coupled with the said signal at a cupling circuit 6 and transmitted to an information transmission line 7 consisting of a frequency-division multiplex converters. Further, a signal inputted at a receiving end IN is branched at a distribution circuit 8 and transmitted to a multiplication detecting circuit 14 via band pass filters 9, 12 and waveform converting circuits 10, 13 and another is transmitted further via a multiplying circuit 11, to detect delay distortion. The number of steps in a delay distortion equalizing circuit 17 corresponding to the delay distortion is discriminated at a logical circuit 16 and the number of stages is controlled for automatic equalization.
JP8981880A 1980-07-01 1980-07-01 Automatic equalizing system for line delay distortion Pending JPS5715538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8981880A JPS5715538A (en) 1980-07-01 1980-07-01 Automatic equalizing system for line delay distortion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8981880A JPS5715538A (en) 1980-07-01 1980-07-01 Automatic equalizing system for line delay distortion

Publications (1)

Publication Number Publication Date
JPS5715538A true JPS5715538A (en) 1982-01-26

Family

ID=13981321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8981880A Pending JPS5715538A (en) 1980-07-01 1980-07-01 Automatic equalizing system for line delay distortion

Country Status (1)

Country Link
JP (1) JPS5715538A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2530099A1 (en) * 1982-07-08 1984-01-13 Telecommunications Sa Device for equalising a digital signal transmitted by a line section

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514365A (en) * 1974-07-05 1976-01-14 Nakamura Kikai Seisakusho Juge TATAMIOMOTEJIDOSHOTSUKINIOKERU TATAMIOMOTENO RYOMECHOSETSUSEISHOKUSOCHI
JPS5412508A (en) * 1977-06-29 1979-01-30 Toshiba Corp Information transmitting system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514365A (en) * 1974-07-05 1976-01-14 Nakamura Kikai Seisakusho Juge TATAMIOMOTEJIDOSHOTSUKINIOKERU TATAMIOMOTENO RYOMECHOSETSUSEISHOKUSOCHI
JPS5412508A (en) * 1977-06-29 1979-01-30 Toshiba Corp Information transmitting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2530099A1 (en) * 1982-07-08 1984-01-13 Telecommunications Sa Device for equalising a digital signal transmitted by a line section

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