JPS57111135A - Signal leading-in system of equalizing system - Google Patents

Signal leading-in system of equalizing system

Info

Publication number
JPS57111135A
JPS57111135A JP55188219A JP18821980A JPS57111135A JP S57111135 A JPS57111135 A JP S57111135A JP 55188219 A JP55188219 A JP 55188219A JP 18821980 A JP18821980 A JP 18821980A JP S57111135 A JPS57111135 A JP S57111135A
Authority
JP
Japan
Prior art keywords
signal
circuit
phase
output
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55188219A
Other languages
Japanese (ja)
Inventor
Takashi Kako
Shigeyuki Umigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55188219A priority Critical patent/JPS57111135A/en
Publication of JPS57111135A publication Critical patent/JPS57111135A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
    • H04L27/2273—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals associated with quadrature demodulation, e.g. Costas loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To lead in a deteriorated circuit easily by use of a deciding reference, by providing a sensitive band on a phase plane of an equalizing output signal, and leading in a receiving signal by only an error signal discriminated by the sensitive band. CONSTITUTION:An input signal is inputted to an equalizer 11, its phase and amplitude are equalized, this output signal is inputted to a deciding circuit 13 through a multiplying part 12, and an error between a decided value and an equalized value is outputted from a subtracting part 14. This output is inputted to a carrier automatic position adjusting circuit CAPC15, and integration for removing the offset and jitter of frequency, and a variation of phase is executed. An output of this circuit 15 is fed back so that a phase difference provided on the circuit 13 through the multiplying part 12, also this output is inputtd to a multiplying part 16, is multiplied by the error signal from the subtracting part 14, is fed back to the equalizer 11, and phase of a receiving carrier signal is set up atuomatically to a reference signal. In this case, the receiving signal is led in instantaneously by supplying an initializing signal by a CACP initializing circuit 10, and feeding it back to the multiplying part 12.
JP55188219A 1980-12-27 1980-12-27 Signal leading-in system of equalizing system Pending JPS57111135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188219A JPS57111135A (en) 1980-12-27 1980-12-27 Signal leading-in system of equalizing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188219A JPS57111135A (en) 1980-12-27 1980-12-27 Signal leading-in system of equalizing system

Publications (1)

Publication Number Publication Date
JPS57111135A true JPS57111135A (en) 1982-07-10

Family

ID=16219846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188219A Pending JPS57111135A (en) 1980-12-27 1980-12-27 Signal leading-in system of equalizing system

Country Status (1)

Country Link
JP (1) JPS57111135A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5970027A (en) * 1982-09-13 1984-04-20 コミユニケ−シヨンズ・サテライト・コ−ポレ−シヨン Adaptive equalizer and signal processor
US4679208A (en) * 1984-07-31 1987-07-07 Ricoh Company, Ltd. Equalization system tuning device which updates equalizer coefficients based on selected decision regions
US5598433A (en) * 1992-01-31 1997-01-28 Fujitsu Limited Automatic equalizer and data mode convergence method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5970027A (en) * 1982-09-13 1984-04-20 コミユニケ−シヨンズ・サテライト・コ−ポレ−シヨン Adaptive equalizer and signal processor
US4679208A (en) * 1984-07-31 1987-07-07 Ricoh Company, Ltd. Equalization system tuning device which updates equalizer coefficients based on selected decision regions
US5598433A (en) * 1992-01-31 1997-01-28 Fujitsu Limited Automatic equalizer and data mode convergence method

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