JPS57154980A - Interlacing circuit - Google Patents

Interlacing circuit

Info

Publication number
JPS57154980A
JPS57154980A JP56041203A JP4120381A JPS57154980A JP S57154980 A JPS57154980 A JP S57154980A JP 56041203 A JP56041203 A JP 56041203A JP 4120381 A JP4120381 A JP 4120381A JP S57154980 A JPS57154980 A JP S57154980A
Authority
JP
Japan
Prior art keywords
signal
display
memory
enlarged
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56041203A
Other languages
Japanese (ja)
Other versions
JPS6343949B2 (en
Inventor
Masaaki Fujita
Yoshio Yasumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56041203A priority Critical patent/JPS57154980A/en
Publication of JPS57154980A publication Critical patent/JPS57154980A/en
Publication of JPS6343949B2 publication Critical patent/JPS6343949B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Studio Circuits (AREA)

Abstract

PURPOSE:To ensure a smooth display of the vertical direction, by providing an address switching circuit to switch the reading address of a video signal memory and then varying the interlacing interpolation sequence in case the display is enlarged. CONSTITUTION:The video signal is written into a memory by the output of a vertical writing address counter 10 with a horizontal synchronizing signal HD used as a clock. In case the display is enlarged, the signal HD is divided by just the enlargement coefficient L to be applied to a delaying circuit 14. Thus a signal 17 which is shifted by an amount equivalent to a horizontal scan of 1/2L or + or -1/2L stage. The signal 17 is switched by a field discriminating signal 18 through a changeover switch along with a 1/2L signal 16 to be supplied to a reading address counter 11 in the form of a clock. The output of the counter 11 is supplied to a memory through an address switch 15. Thus the vertical direction can be made smooth for an enlarged display.
JP56041203A 1981-03-19 1981-03-19 Interlacing circuit Granted JPS57154980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56041203A JPS57154980A (en) 1981-03-19 1981-03-19 Interlacing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56041203A JPS57154980A (en) 1981-03-19 1981-03-19 Interlacing circuit

Publications (2)

Publication Number Publication Date
JPS57154980A true JPS57154980A (en) 1982-09-24
JPS6343949B2 JPS6343949B2 (en) 1988-09-01

Family

ID=12601852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56041203A Granted JPS57154980A (en) 1981-03-19 1981-03-19 Interlacing circuit

Country Status (1)

Country Link
JP (1) JPS57154980A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021677A (en) * 1983-07-15 1985-02-04 Sony Corp Picture signal converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021677A (en) * 1983-07-15 1985-02-04 Sony Corp Picture signal converter
JPH0574272B2 (en) * 1983-07-15 1993-10-18 Sony Corp

Also Published As

Publication number Publication date
JPS6343949B2 (en) 1988-09-01

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