JPS57152593A - Insulated gate type storing circuit - Google Patents

Insulated gate type storing circuit

Info

Publication number
JPS57152593A
JPS57152593A JP56038490A JP3849081A JPS57152593A JP S57152593 A JPS57152593 A JP S57152593A JP 56038490 A JP56038490 A JP 56038490A JP 3849081 A JP3849081 A JP 3849081A JP S57152593 A JPS57152593 A JP S57152593A
Authority
JP
Japan
Prior art keywords
electric potential
transistor
insulated gate
raised
condition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56038490A
Other languages
Japanese (ja)
Other versions
JPS6216476B2 (en
Inventor
Takashi Uno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56038490A priority Critical patent/JPS57152593A/en
Publication of JPS57152593A publication Critical patent/JPS57152593A/en
Publication of JPS6216476B2 publication Critical patent/JPS6216476B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To realize sure operation of the power-on-reset function, by using an enhancement type insulated gate field effect transistor (FET). CONSTITUTION:An enhancement type insulated gate FET Q7 is connected as shown in the diagram. When the power source is off, the electric potential of all contacts is equal to that of earthing points 3 under balanced condition. When the powr source is on, an output terminal 1 is raised to the supply voltage Vb side. Then, a transistor Q5 is made into non-conductive state after the circuit is reversed to the 2nd stable condition by the conduction of the transistor Q5. When the power supply is cut after this condition, transistors Q2 and Q4 are made into non-conductive state but the transistor Q7 is conducted when the electric potential of the power source D drops to VD-2VT1 and discharges. Therefore, the electric potential at an output terminal 2 is raised to VT1. Accordingly, when the power source is again turned on, the electric potential at the putput terminal 2 is scarely raised to VD-VT1 level, and, when the logical threshold of the 1st inverter is high, the electric potential of the output 2 drops and becomes the initial condition.
JP56038490A 1981-03-17 1981-03-17 Insulated gate type storing circuit Granted JPS57152593A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56038490A JPS57152593A (en) 1981-03-17 1981-03-17 Insulated gate type storing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56038490A JPS57152593A (en) 1981-03-17 1981-03-17 Insulated gate type storing circuit

Publications (2)

Publication Number Publication Date
JPS57152593A true JPS57152593A (en) 1982-09-20
JPS6216476B2 JPS6216476B2 (en) 1987-04-13

Family

ID=12526698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56038490A Granted JPS57152593A (en) 1981-03-17 1981-03-17 Insulated gate type storing circuit

Country Status (1)

Country Link
JP (1) JPS57152593A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59152597A (en) * 1983-02-18 1984-08-31 Nec Corp Memory circuit
US4594688A (en) * 1981-09-10 1986-06-10 Nippon Electric Co., Ltd. Power supply circuit for flip-flop memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS=1977M10 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594688A (en) * 1981-09-10 1986-06-10 Nippon Electric Co., Ltd. Power supply circuit for flip-flop memory
JPS59152597A (en) * 1983-02-18 1984-08-31 Nec Corp Memory circuit
JPH0241116B2 (en) * 1983-02-18 1990-09-14 Nippon Electric Co

Also Published As

Publication number Publication date
JPS6216476B2 (en) 1987-04-13

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