JPS6216476B2 - - Google Patents
Info
- Publication number
- JPS6216476B2 JPS6216476B2 JP56038490A JP3849081A JPS6216476B2 JP S6216476 B2 JPS6216476 B2 JP S6216476B2 JP 56038490 A JP56038490 A JP 56038490A JP 3849081 A JP3849081 A JP 3849081A JP S6216476 B2 JPS6216476 B2 JP S6216476B2
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- circuit
- power
- potential
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 claims description 4
- 230000004044 response Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Description
【発明の詳細な説明】
この発明は絶縁ゲート電界効果素子を用いた記
憶回路装置に係り、特に安定した動作をするパワ
ー・オン・リセツト回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit device using an insulated gate field effect device, and particularly to a power-on reset circuit that operates stably.
従来集積回路装置では、電源を入れた場合、内
部状態を初期状態に設定するパワー・オン・リセ
ツト型記憶回路が多用されている。 Conventional integrated circuit devices often use power-on reset type memory circuits that set the internal state to an initial state when the power is turned on.
以下従来の回路の動作を第１図の回路図に従い
説明する。 The operation of the conventional circuit will be explained below with reference to the circuit diagram of FIG.
第１のインバータにおいてデプリーシヨン型の
第１の負荷トランジスタＱ１はドレインを電源Ｄ
側に、ゲート及びソースを出力１に接続してあ
る。第２のインバータのエンハンスメント型負荷
トランジスタＱ２はドレイン及びゲートを電源Ｄ
側に、ソースを出力２に接続してある。増幅用ト
ランジスタＱ３のドレイン、ゲート、ソースはそ
れぞれ１，２、接地３に、同じく増幅トランジス
タＱ４のドレイン、ゲート、ソースはそれぞれ
２，１，３に接続され、全体として２種類のイン
バータが正帰還する様に構成されている。又、出
力端子１，２と接地３間には配線容量等の浮遊容
量及びMOS容量で成るＣ１，Ｃ２が存在してい
る。又、出力１（あるいは２）と接地３間に書込
み用トランジスタＱ５（あるいはＱ６）が接続さ
れている。 In the first inverter, a depletion type first load transistor Q1 has a drain connected to a power source D.
On the side, the gate and source are connected to output 1. The enhancement type load transistor Q2 of the second inverter has its drain and gate connected to the power supply D.
On the side, the source is connected to output 2. The drain, gate, and source of the amplification transistor Q3 are connected to 1, 2, and ground 3, respectively, and the drain, gate, and source of the amplification transistor Q4 are connected to 2, 1, and 3, respectively, so that two types of inverters as a whole are connected to positive feedback. It is configured to do so. Further, between the output terminals 1 and 2 and the ground 3, there exist C1 and C2 consisting of stray capacitance such as wiring capacitance and MOS capacitance. Further, a write transistor Q5 (or Q6) is connected between output 1 (or 2) and ground 3.
電源が切れて接地点電位の場合、平衡状態では
すべての接点は接地点３の電位と同じであるた
め、電源が入つた瞬間、Ｑ３，Ｑ４は非導通とな
つている（Ｑ５，Ｑ６も非導通状態とする。）。こ
のため、Ｑ１，Ｑ２の導通時抵抗R1，R2及びＣ
１，Ｃ２によつて決定されるR1C1、R2C2の時定
数に従い、出力端１，２はＱ４あるいはＱ３のし
きい値電圧ＶT1に達するまで充電される。R1C1
≪R2C2と設計されている場合、出力端１は先に
ＶT1に達するためＱ４は導通し始める。一般に増
幅用トランジスタの導通抵抗は負荷トランジスタ
の導通抵抗より十分小さいため、出力端２の電位
上昇は小さくなる。一方、Ｑ３は非導通のままな
ので出力１は更に充電されＱ４の導通抵抗を更に
下げ出力端２の電位を下降させる様に働く。 When the power is turned off and the potential is at the ground point, all contacts are at the same potential as the ground point 3 in an equilibrium state, so the moment the power is turned on, Q3 and Q4 are non-conducting (Q5 and Q6 are also non-conducting). conductive state). Therefore, when Q1 and Q2 are conductive, the resistances R 1 , R 2 and C
According to the time constants R 1 C 1 and R 2 C 2 determined by C 1 and C2, the outputs 1 and 2 are charged until they reach the threshold voltage V T1 of Q4 or Q3. R 1 C 1
If it is designed as <<R 2 C 2 , output terminal 1 reaches V T1 first, so Q4 starts to conduct. Generally, the conduction resistance of the amplification transistor is sufficiently smaller than the conduction resistance of the load transistor, so that the potential rise at the output terminal 2 is small. On the other hand, since Q3 remains non-conductive, the output 1 is further charged, further lowering the conduction resistance of Q4 and lowering the potential at the output terminal 2.
以上の如く、R1C1≪R2C2となる様に設計され
た回路では平衡状態で電源を入れた場合、出力端
１は目的とする初期状態である電源電位ＶD側に
必ず引上げられる。 As mentioned above, in a circuit designed so that R 1 C 1 ≪ R 2 C 2 , when the power is turned on in a balanced state, the output terminal 1 will always be pulled up to the power supply potential V D side, which is the desired initial state. It will be done.
ところで、上記初期状態に設定された後、上記
書込み用トランジスタＱ５を導通させてC1の電
荷を放電し出力端１を接地電位側に下げると、出
力端２はＱ２により充電され、十分時間が経過し
た後は出力端２の電位はＶD−ＶT1となり、Ｑ５
を非導通にしてもこの状態（第２の安定状態）を
保つ。さて、上記第２の安定状態の後電源Ｄを接
地電位に落とすとＱ２，Ｑ４は非導通となつてい
るため、出力端２の電位は保持される事になる。
保持時間は、漏洩電流ＩLとC2により決まるがＩ
Lは通常十分小さく、かつC2は大きく設定してい
るため十分長くなる。従つて保持された状態で再
び電源が入ると本回路は第２の安定状態のままと
なり、目的とする初期状態に設定されない。 By the way, after the above initial state is set, when the write transistor Q5 is made conductive to discharge the charge of C1 and lower the output terminal 1 to the ground potential side, the output terminal 2 is charged by Q2, and it takes a sufficient time. After the elapsed time, the potential of output terminal 2 becomes V D -V T1 , and Q5
This state (second stable state) is maintained even if it is made non-conductive. Now, when the power source D is dropped to the ground potential after the second stable state, Q2 and Q4 are non-conductive, so the potential of the output terminal 2 is held.
The holding time is determined by the leakage current I L and C2 , but I
Since L is usually sufficiently small and C 2 is set large, it is sufficiently long. Therefore, if the power is turned on again in the maintained state, the circuit remains in the second stable state and is not set to the intended initial state.
以上の如く、従来回路では電源の開閉間隔が短
い場合、目的とするパワー・オン・リセツト機能
が働かない欠点があつた。 As described above, the conventional circuit has the disadvantage that the intended power-on reset function does not work when the power supply opening/closing interval is short.
本発明は上記従来回路の欠点を改善し、パワ
ー・オン・リセツト機能の確実な動作を可能とす
る絶縁ゲート型記憶回路を提供するものである。 The present invention improves the drawbacks of the conventional circuit and provides an insulated gate type memory circuit which enables reliable operation of the power-on reset function.
本発明は第１のインバータおよび第２のインバ
ータを有するフリツプ・フロツプ回路と、電源投
入に応答して前記第１のインバータの出力点を前
記第２のインバータの出力点よりも先に充電する
回路とを有する絶縁ゲート型記憶回路において、
電源遮断に応答して前記第２のインバータの出力
点電位を強制的に放電する回路を設けたことを特
徴とするものである。また前記放電回路は一端を
前記第２のインバータの出力点に、他端を電源の
一端に接続した電界効果トランジスタを含むこと
を特徴とする。 The present invention provides a flip-flop circuit having a first inverter and a second inverter, and a circuit for charging the output point of the first inverter before the output point of the second inverter in response to power-on. In an insulated gate type memory circuit having
The present invention is characterized in that a circuit is provided for forcibly discharging the potential at the output point of the second inverter in response to power cutoff. Further, the discharge circuit is characterized in that it includes a field effect transistor having one end connected to the output point of the second inverter and the other end connected to one end of the power supply.
次に、本発明をその実施例に従い、図面を参照
して説明する。 Next, the present invention will be described according to embodiments thereof and with reference to the drawings.
第２図は本発明の一実施例を示す回路接続図で
あり、エンハンスメント型絶縁ゲート電界効果ト
ランジスタQ7を、トランジスタQ2と並列に、ゲ
ートが出力端２になるように接続して挿入されて
いることを除いて第１図の従来例と同じである。
電源が切れている場合、平衡状態ではすべての接
点は接地点３電位と同じである。 FIG. 2 is a circuit connection diagram showing an embodiment of the present invention, in which an enhancement type insulated gate field effect transistor Q 7 is connected and inserted in parallel with a transistor Q 2 so that its gate becomes the output terminal 2. This is the same as the conventional example shown in FIG. 1, except that
When the power is off, in equilibrium all contacts are at the same potential as ground point 3.
電源が入つた場合、Ｑ３，Ｑ４及びＱ７はオフ
しているため、上記従来回路と同じ動作で出力端
１は電源電位ＶD側に引上げられる。上記初期状
態が定まつた後、トランジスタＱ５を導通させる
事により第２の安定状態（出力１を接地電位側に
下げ、出力２をＶD−ＶT1に引き上げる）に反転
させた後、トランジスタＱ５を非導通にさせる。
この後電源を切る（接地点電位に落とす）と、ト
ランジスタＱ２，Ｑ４は非導通となつているが、
Ｑ７は電源Ｄの電位がＶD−2VT1まで落ちた時、
導通し、出力端２に充電された電荷を放電する。
このため出力端２電位はＶT1まで急速に回復す
る。従つて再び電源が入つた場合、前記時定数が
R1C1≪R2C2であり、更に上記第２のインバータ
はエンハンスメント型負荷であるため出力端２の
電位はＶD−ＶT付近では極めて上昇しにくく、前
記第１のインバータの論理しきい値が高ければＱ
４の導通により出力２の電位は下げられ初期状態
に設定される。 When the power is turned on, since Q3, Q4, and Q7 are off, the output terminal 1 is pulled up to the power supply potential V D in the same operation as the conventional circuit described above. After the above initial state is established, the transistor Q5 is turned on to invert to the second stable state (output 1 is lowered to the ground potential side and output 2 is raised to V D -V T1 ), and then the transistor Q5 is turned on. becomes non-conductive.
After this, when the power is turned off (dropped to the ground potential), transistors Q2 and Q4 are non-conductive.
Q7 is when the potential of power supply D drops to V D -2V T1 ,
It becomes conductive and discharges the charge stored in the output terminal 2.
Therefore, the output terminal 2 potential quickly recovers to V T1 . Therefore, when the power is turned on again, the above time constant is
R 1 C 1 ≪ R 2 C 2 , and since the second inverter is an enhancement type load, the potential at the output terminal 2 is extremely difficult to rise near V D −V T , and the logic of the first inverter is If the threshold is high, Q
4 becomes conductive, the potential of output 2 is lowered and set to the initial state.
なお、トランジスタＱ７のしきい値電圧ＶT0の
絶対値を他のエンハンスメント型トランジスタよ
り低く設定した場合、前記第２の安定状態が保た
れた後、電源線の電位がＶD−ＶT1−ＶT0まで落
ちるとＱ７は導通し、出力２の電位はＶT0まで急
速に下がる。従つて再び電源が入つた場合、出力
２はＶT1まで充電されにくく、その結果更に確実
に目的とする初期状態が得られる。 Note that when the absolute value of the threshold voltage V T0 of the transistor Q7 is set lower than that of other enhancement type transistors, the potential of the power supply line becomes V D -V T1 -V after the second stable state is maintained. When the voltage drops to T0 , Q7 becomes conductive and the potential of output 2 rapidly drops to V T0 . Therefore, when the power is turned on again, the output 2 is unlikely to be charged up to V T1 , and as a result, the desired initial state can be obtained more reliably.
以上に述べた如く、本発明により、従来技術で
は得られなかつたパワー・オン・リセツト機能の
確実な動作を達成する事が出来る。 As described above, the present invention makes it possible to achieve reliable operation of the power-on reset function, which was not possible with the prior art.
第１図は従来の絶縁ゲート型記憶回路の回路接
続図、第２図は本発明の一実施例を示す回路接続
図である。
図において、Ｑ１……デプリケーシヨン型トラ
ンジスタ、Ｑ２，Ｑ３，Ｑ４，Ｑ５，Ｑ６……エ
ンハンスメント型トランジスタ、Ｑ７……Q2〜
Q6のしきい値電圧と同じあるいは絶対値の低い
エンハンスメント型トランジスタ、Ｄ……電源
線、１，２……出力端、３……接地点、C1，C2
……浮遊容量あるいはゲート容量である。
FIG. 1 is a circuit connection diagram of a conventional insulated gate type memory circuit, and FIG. 2 is a circuit connection diagram showing an embodiment of the present invention. In the figure, Q1...deplication type transistor, Q2, Q3, Q4, Q5, Q6...enhancement type transistor, Q7...Q2 ~
Enhancement type transistor with the same or lower absolute value than the threshold voltage of Q 6 , D...power line, 1, 2...output terminal, 3...ground point, C 1 , C 2
...This is floating capacitance or gate capacitance.
Claims (1)
有するフリツプ・フロツプ回路と、電源投入に応
答して前記第１のインバータの出力点を前記第２
のインバータの出力点よりも先に充電する回路と
を有する絶縁ゲート型記憶回路において、電源遮
断に応答して前記第２のインバータの出力点電位
を強制的に放電する回路を設けたことを特徴とす
る絶縁ゲート型記憶回路。 ２ 前記放電回路は一端を前記第２のインバータ
の出力点に、他端を電源の一端に接続した電界効
果トランジスタを含むことを特徴とする特許請求
の範囲第１項記載の絶縁ゲート型記憶回路。[Scope of Claims] 1. A flip-flop circuit having a first inverter and a second inverter;
The insulated gate memory circuit has a circuit that charges the output point of the second inverter before the output point of the second inverter, and is characterized by being provided with a circuit that forcibly discharges the potential of the output point of the second inverter in response to power cutoff. An insulated gate type memory circuit. 2. The insulated gate type memory circuit according to claim 1, wherein the discharge circuit includes a field effect transistor having one end connected to the output point of the second inverter and the other end connected to one end of the power supply. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56038490A JPS57152593A (en) | 1981-03-17 | 1981-03-17 | Insulated gate type storing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56038490A JPS57152593A (en) | 1981-03-17 | 1981-03-17 | Insulated gate type storing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57152593A JPS57152593A (en) | 1982-09-20 |
| JPS6216476B2 true JPS6216476B2 (en) | 1987-04-13 |
Family
ID=12526698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56038490A Granted JPS57152593A (en) | 1981-03-17 | 1981-03-17 | Insulated gate type storing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57152593A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5845695A (en) * | 1981-09-10 | 1983-03-16 | Nec Corp | Insulation gate type storage circuit |
| JPS59152597A (en) * | 1983-02-18 | 1984-08-31 | Nec Corp | Memory circuit |
-
1981
- 1981-03-17 JP JP56038490A patent/JPS57152593A/en active Granted
Non-Patent Citations (1)
| Title |
|---|
| IEEE JOURNAL OF SOLID-STATE CIRCUITS=1977M10 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57152593A (en) | 1982-09-20 |
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