JPS57148345A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57148345A
JPS57148345A JP3316181A JP3316181A JPS57148345A JP S57148345 A JPS57148345 A JP S57148345A JP 3316181 A JP3316181 A JP 3316181A JP 3316181 A JP3316181 A JP 3316181A JP S57148345 A JPS57148345 A JP S57148345A
Authority
JP
Japan
Prior art keywords
substrate
single crystal
region
over
500kev
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3316181A
Other languages
Japanese (ja)
Inventor
Michiro Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3316181A priority Critical patent/JPS57148345A/en
Publication of JPS57148345A publication Critical patent/JPS57148345A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To acquire a device of high speed and low power dissipation, by ion- implanting an element to make an insulator on an Si substrate at accelerating voltage over 500keV with injection over 10<16> particles/cm<2>, forming a shallow insulating layer under the substrate through heat treatment, and making epitaxial growth of a thin film for semiconductor element formation of the same ingredient as the substrate thereupon. CONSTITUTION:O2 ions are implanted in an Si single crystal substrate 8 at accelerating voltage over 500keV with implantation over 10<16> particles/cm<2>. A region 9 filled in large quantity with O2 is formed under the surface of substrate 8 deeper than 1mum. A surface layer 8' of the substrate 8 is left as single crystal without losing its crystallization because of high-energy ion implantation. Next, the region 9 is changed into an SiO2 insulating layer through heat treatment at 1,000 deg.C, for around three hours. A single crystal layer 8'' is epitaxial- grown on the surface layer 8' with the same ingredient as the substrate 8. Then, the layers 8'' and 8' are patterned as necessary, covered with an SiO2 film 12, and used as an element formation region.
JP3316181A 1981-03-10 1981-03-10 Manufacture of semiconductor device Pending JPS57148345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3316181A JPS57148345A (en) 1981-03-10 1981-03-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3316181A JPS57148345A (en) 1981-03-10 1981-03-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57148345A true JPS57148345A (en) 1982-09-13

Family

ID=12378828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3316181A Pending JPS57148345A (en) 1981-03-10 1981-03-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57148345A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003852A (en) * 2008-06-19 2010-01-07 Sumco Corp Epitaxial wafer and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003852A (en) * 2008-06-19 2010-01-07 Sumco Corp Epitaxial wafer and method of manufacturing the same

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