JPS57139841A - Interruption control system - Google Patents

Interruption control system

Info

Publication number
JPS57139841A
JPS57139841A JP2508381A JP2508381A JPS57139841A JP S57139841 A JPS57139841 A JP S57139841A JP 2508381 A JP2508381 A JP 2508381A JP 2508381 A JP2508381 A JP 2508381A JP S57139841 A JPS57139841 A JP S57139841A
Authority
JP
Japan
Prior art keywords
data
received data
buffer
contents
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2508381A
Other languages
Japanese (ja)
Inventor
Osamu Wada
Yasuyuki Wakabayashi
Kenji Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kawasaki Heavy Industries Ltd
Panafacom Ltd
Fuji Facom Corp
Kawasaki Motors Ltd
Original Assignee
Kawasaki Heavy Industries Ltd
Panafacom Ltd
Kawasaki Jukogyo KK
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Heavy Industries Ltd, Panafacom Ltd, Kawasaki Jukogyo KK, Fuji Facom Corp filed Critical Kawasaki Heavy Industries Ltd
Priority to JP2508381A priority Critical patent/JPS57139841A/en
Publication of JPS57139841A publication Critical patent/JPS57139841A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Abstract

PURPOSE:To reduce a load of a processor of the center side, and to elevate the efficiency of the whole system, by generating an interruption only when contents of a telegram of a state of the other party have been varied, and when a line fault has occurred, when receiving a data. CONSTITUTION:A data D passes through a communication line 1, reaches a line adaptor 2, and is stored in a buffer 3. A detecting circuit 4 has a means for supervising a data in the buffer 3 whenever it is received, and detecting a difference of data contents between a new received data and an old received data. When receiving a data, the detecting circuit 4 checks a difference between the new received data and the old received data in the buffer 3, and sends out an interruption signal 1 to a processor 8 only in case when a variation of the data contents has been detected. Therefore, the processor generates a control signal, transfers a new received data D in the buffer 3 to a data area 6 of a main storage device 7, and after that, processes this received data.
JP2508381A 1981-02-23 1981-02-23 Interruption control system Pending JPS57139841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2508381A JPS57139841A (en) 1981-02-23 1981-02-23 Interruption control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2508381A JPS57139841A (en) 1981-02-23 1981-02-23 Interruption control system

Publications (1)

Publication Number Publication Date
JPS57139841A true JPS57139841A (en) 1982-08-30

Family

ID=12156029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2508381A Pending JPS57139841A (en) 1981-02-23 1981-02-23 Interruption control system

Country Status (1)

Country Link
JP (1) JPS57139841A (en)

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