JPS5713550A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5713550A
JPS5713550A JP8660080A JP8660080A JPS5713550A JP S5713550 A JPS5713550 A JP S5713550A JP 8660080 A JP8660080 A JP 8660080A JP 8660080 A JP8660080 A JP 8660080A JP S5713550 A JPS5713550 A JP S5713550A
Authority
JP
Japan
Prior art keywords
address
circuit
memory device
sent
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8660080A
Other languages
Japanese (ja)
Inventor
Isamu Yasui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8660080A priority Critical patent/JPS5713550A/en
Publication of JPS5713550A publication Critical patent/JPS5713550A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To get rid of an access time, and to prevent a decline of a processing functon, by converting a data to a memory address which has been designated by a program, and accessing it to a memory device which is different in an instruction and a data, in a data processing equipment of an advance control system. CONSTITUTION:When an instruction is read out, and a data is read out and written, an instruction read-out controlling circuit 1 and a data read-out and write controlling circuit 2 are operated, and output an access request to a memory request receiving circuit 4. Also, it is sent to an address converting circuit 5, too, and the request is discriminated by a receiving signal from the receiving circuit 4. On the other hand, a memory device address is sent to the converting circuit 5 from a memory address preparing circuit 3, the converting circuit 5 converts the memory device address in accordance with a discriminated request of the controlling circuit 1, 2, it is sent to a memory device enable preparing circuit 6, is decoded to enable signals EN0-ENn, and is sent to the memory device separately. Also, an address in the memory device is address-converted, too, in accordance with a request, and is sent to the memory address as it is.
JP8660080A 1980-06-27 1980-06-27 Memory control system Pending JPS5713550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8660080A JPS5713550A (en) 1980-06-27 1980-06-27 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8660080A JPS5713550A (en) 1980-06-27 1980-06-27 Memory control system

Publications (1)

Publication Number Publication Date
JPS5713550A true JPS5713550A (en) 1982-01-23

Family

ID=13891496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8660080A Pending JPS5713550A (en) 1980-06-27 1980-06-27 Memory control system

Country Status (1)

Country Link
JP (1) JPS5713550A (en)

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