JPS57134750A - Relation algebra operating device - Google Patents

Relation algebra operating device

Info

Publication number
JPS57134750A
JPS57134750A JP56019303A JP1930381A JPS57134750A JP S57134750 A JPS57134750 A JP S57134750A JP 56019303 A JP56019303 A JP 56019303A JP 1930381 A JP1930381 A JP 1930381A JP S57134750 A JPS57134750 A JP S57134750A
Authority
JP
Japan
Prior art keywords
key
tuple
memory
signal line
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56019303A
Other languages
Japanese (ja)
Inventor
Yasumitsu Oda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56019303A priority Critical patent/JPS57134750A/en
Publication of JPS57134750A publication Critical patent/JPS57134750A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

PURPOSE:To achieve effective use of memories, by registrating new keys only to an associate memory device together with memory storage location information of a tuple main body and erasing unnecessary tuple from a memory and a buffer in a relational algebraic operator. CONSTITUTION:When a main controller 25 gives a tranfer request of a key and a tuple (element of a set) to a signal line 26, the key is outputted to a signal line 10 and the tuple main body is on a signal line 11 respectively and stored to a corresponding location of a tuple main body storage memory 15 and buffer 14 to be instructed 18, 19. In an associative memory logical device 12, if the key of the signal line 10 is registrated in an associative memory device 13 and a necessary/unnecessary signal is given to signal lines 22, 23. In case of registrated key, the transfer request of the next key is given to a device 25 and the result of retirieval and tuple storage location are given to a retrieval result storage buffer 16. In case of unregistrated key, the device 12 transfers an overflow signal of the memory 13 to the device 25 or the transfer request of the next key is outputted.
JP56019303A 1981-02-12 1981-02-12 Relation algebra operating device Pending JPS57134750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56019303A JPS57134750A (en) 1981-02-12 1981-02-12 Relation algebra operating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56019303A JPS57134750A (en) 1981-02-12 1981-02-12 Relation algebra operating device

Publications (1)

Publication Number Publication Date
JPS57134750A true JPS57134750A (en) 1982-08-20

Family

ID=11995646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56019303A Pending JPS57134750A (en) 1981-02-12 1981-02-12 Relation algebra operating device

Country Status (1)

Country Link
JP (1) JPS57134750A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4780810A (en) * 1984-05-25 1988-10-25 Hitachi, Ltd. Data processor with associative memory storing vector elements for vector conversion

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4780810A (en) * 1984-05-25 1988-10-25 Hitachi, Ltd. Data processor with associative memory storing vector elements for vector conversion

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