JPS6461837A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS6461837A
JPS6461837A JP62216322A JP21632287A JPS6461837A JP S6461837 A JPS6461837 A JP S6461837A JP 62216322 A JP62216322 A JP 62216322A JP 21632287 A JP21632287 A JP 21632287A JP S6461837 A JPS6461837 A JP S6461837A
Authority
JP
Japan
Prior art keywords
pointer
block
stack
address
pointed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62216322A
Other languages
Japanese (ja)
Inventor
Kenichi Maeda
Mitsuo Saito
Takeshi Aikawa
Mitsuyoshi Okamura
Tsukasa Matoba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62216322A priority Critical patent/JPS6461837A/en
Publication of JPS6461837A publication Critical patent/JPS6461837A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To write data with no useless action, by comparing a pointer with an access address and updating the pointer value based on the result of said comparison. CONSTITUTION:A V pointer 4 is updated by an updating means 6 based on the result of a comparing means 5 so that the pointer 4 points the highest one of the blocks containing stack points. The direct accesses are possible to the address and the block M pointed by a stack point since V bits are set at said address and block M. When the stack moves down by two positions, a block N is pointed. In such a case, a control means 7 is actuated so that an action similar to a cache mistake is carried out by the output of the means 5 since a V point is smaller than or equal to an access address. Then the block N is pointed again when the stack moves up by three positions. In this case, a cache mistake is caused without avoiding a block copying action only via a low-speed memory 3 since the V pointer is larger than the access address.
JP62216322A 1987-09-01 1987-09-01 Memory control system Pending JPS6461837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62216322A JPS6461837A (en) 1987-09-01 1987-09-01 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62216322A JPS6461837A (en) 1987-09-01 1987-09-01 Memory control system

Publications (1)

Publication Number Publication Date
JPS6461837A true JPS6461837A (en) 1989-03-08

Family

ID=16686711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62216322A Pending JPS6461837A (en) 1987-09-01 1987-09-01 Memory control system

Country Status (1)

Country Link
JP (1) JPS6461837A (en)

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