JPS57133788A - Dropout compensating circuit - Google Patents
Dropout compensating circuitInfo
- Publication number
- JPS57133788A JPS57133788A JP56019692A JP1969281A JPS57133788A JP S57133788 A JPS57133788 A JP S57133788A JP 56019692 A JP56019692 A JP 56019692A JP 1969281 A JP1969281 A JP 1969281A JP S57133788 A JPS57133788 A JP S57133788A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- output
- dropout
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/87—Regeneration of colour television signals
- H04N9/88—Signal drop-out compensation
- H04N9/882—Signal drop-out compensation the signal being a composite colour television signal
Abstract
PURPOSE:To achieve compensating operation for dropout and to prevent distortion in hue, by delaying a reproduced color video signal by one horizontal scanning period and selecting one side of an input signal and an output signal for the delay circuit. CONSTITUTION:A reproduced video signal from a reproducing FM color video input terminal 1 is applied to a 1H delay circuit 4 via terminals A, C, and applied to a reproducing FM color video signal output terminal 10 with one horizontal scanning period delay. The output of the circuit 4 is applied to a contact C of the circuit 5, a video signal at the terminal 1 is applied to a dropout detection circuit 6, and a detection signal (c) is outputted when the dropout is detected. When a synchronizing signal (a) from a reproducing horizontal synchronizing signal input terminal 2 is applied to a reset terminal of an FF8, a kick pulse (e) from a kick signal input terminal 3 is applied to a gate circuit 7, the signal (c) is applied to the FF8 during the pulse period, the output (d) of the FF8 and the signal (c) are logicallly summed at an OR circuit 9, the output of the circuit 9 switches the circuit 5 and dropout is compensated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56019692A JPS57133788A (en) | 1981-02-13 | 1981-02-13 | Dropout compensating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56019692A JPS57133788A (en) | 1981-02-13 | 1981-02-13 | Dropout compensating circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57133788A true JPS57133788A (en) | 1982-08-18 |
JPS6315796B2 JPS6315796B2 (en) | 1988-04-06 |
Family
ID=12006297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56019692A Granted JPS57133788A (en) | 1981-02-13 | 1981-02-13 | Dropout compensating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57133788A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106030451B (en) | 2014-02-28 | 2021-03-12 | 株式会社半导体能源研究所 | Electronic device |
-
1981
- 1981-02-13 JP JP56019692A patent/JPS57133788A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6315796B2 (en) | 1988-04-06 |
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