JPS57132479A - Synchronizing separation circuit - Google Patents
Synchronizing separation circuitInfo
- Publication number
- JPS57132479A JPS57132479A JP1756881A JP1756881A JPS57132479A JP S57132479 A JPS57132479 A JP S57132479A JP 1756881 A JP1756881 A JP 1756881A JP 1756881 A JP1756881 A JP 1756881A JP S57132479 A JPS57132479 A JP S57132479A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- horizontal synchronizing
- terminal
- signal
- synchronizing signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
Abstract
PURPOSE:To separate and reproduce stably and surely horizontal synchronizing signal against ghost, by using a frequency component of the horizontal synchronizing signal at the part where a video signal component at a vertical blanking period is not in existing. CONSTITUTION:A video signal applied to a terminal l1 is applied to an addition filtering circuit SAA and a low pass filter circuit LPA. The SAA consists of a plurality of delay circuits and an addition circuit adding an input signal and output of each delay circuit, and constitutes a low pass filter, unnecessary harmonics is removed at the LPA, and a fundamental wave component of the vertical and horizontal synchronizing signals is obtained at a terminal l3. Next, a subtraction filter SDF of the next stage consists of a delay circuit and a subtraction circuit, and a frequency component of the horizontal synchronizing signal is obtained at an output terminal l4, and no video signal is in existing to the horizontal synchronizing signal component during the vertical blanking period. The signal at the terminal l4 is applied to a circuit PLP consisting of a PLL circuit via a gate circuit GAT and the reproduced horizontal synchronizing signal is obtained at a terminal l7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1756881A JPS57132479A (en) | 1981-02-10 | 1981-02-10 | Synchronizing separation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1756881A JPS57132479A (en) | 1981-02-10 | 1981-02-10 | Synchronizing separation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57132479A true JPS57132479A (en) | 1982-08-16 |
JPS619787B2 JPS619787B2 (en) | 1986-03-26 |
Family
ID=11947516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1756881A Granted JPS57132479A (en) | 1981-02-10 | 1981-02-10 | Synchronizing separation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57132479A (en) |
-
1981
- 1981-02-10 JP JP1756881A patent/JPS57132479A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS619787B2 (en) | 1986-03-26 |
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