JPS57124940A - Voltage level converting circuit - Google Patents

Voltage level converting circuit

Info

Publication number
JPS57124940A
JPS57124940A JP56009603A JP960381A JPS57124940A JP S57124940 A JPS57124940 A JP S57124940A JP 56009603 A JP56009603 A JP 56009603A JP 960381 A JP960381 A JP 960381A JP S57124940 A JPS57124940 A JP S57124940A
Authority
JP
Japan
Prior art keywords
power supply
circuit
negative power
input
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56009603A
Other languages
Japanese (ja)
Inventor
Satokazu Saito
Isao Kawamoto
Seiichi Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56009603A priority Critical patent/JPS57124940A/en
Publication of JPS57124940A publication Critical patent/JPS57124940A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To achieve the transmission of earth on an SR line even at a failure of a power supply device, by connecting a resistance division circuit for bias supply of a transistor switch to a logical sum circuit inputting an input negative power supply of the power supply device and an input negative power supply o another system. CONSTITUTION:A logical level SR signal 2 outputted from a logical circuit 1 is voltage-converted at a resistance division circuit 5 to control on/off of a PNP transistor (TR) switch 6, allowing to open or ground an SR signal transmission terminal 7. The logical sum between an input negative power supply from a power supply negative voltage input terminal 8 and that from a negative power supply input terminal 9 of a separate system, is taken at a logical sum circuit 10, and the output is applied to one end of the circuit 5 as a negative power supply. If the secondary output voltage of a power supply 3 is opened due to any cause, as far as either one of the negative power supply 8 or 9 is normal, the switch 6 turns on and ground is given to an SR signal transmission terminal 7.
JP56009603A 1981-01-27 1981-01-27 Voltage level converting circuit Pending JPS57124940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56009603A JPS57124940A (en) 1981-01-27 1981-01-27 Voltage level converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56009603A JPS57124940A (en) 1981-01-27 1981-01-27 Voltage level converting circuit

Publications (1)

Publication Number Publication Date
JPS57124940A true JPS57124940A (en) 1982-08-04

Family

ID=11724879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56009603A Pending JPS57124940A (en) 1981-01-27 1981-01-27 Voltage level converting circuit

Country Status (1)

Country Link
JP (1) JPS57124940A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5337549U (en) * 1976-09-07 1978-04-01
JPS5444192A (en) * 1977-09-13 1979-04-07 Toshiba Corp Control red driving system
JPS5525561U (en) * 1978-08-09 1980-02-19

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5337549U (en) * 1976-09-07 1978-04-01
JPS5444192A (en) * 1977-09-13 1979-04-07 Toshiba Corp Control red driving system
JPS5525561U (en) * 1978-08-09 1980-02-19

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