JPS57120296A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS57120296A
JPS57120296A JP617281A JP617281A JPS57120296A JP S57120296 A JPS57120296 A JP S57120296A JP 617281 A JP617281 A JP 617281A JP 617281 A JP617281 A JP 617281A JP S57120296 A JPS57120296 A JP S57120296A
Authority
JP
Japan
Prior art keywords
erasure
cell
source
gate
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP617281A
Other languages
Japanese (ja)
Other versions
JPS6130351B2 (en
Inventor
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP617281A priority Critical patent/JPS57120296A/en
Priority to US06/320,937 priority patent/US4437174A/en
Publication of JPS57120296A publication Critical patent/JPS57120296A/en
Publication of JPS6130351B2 publication Critical patent/JPS6130351B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To prevent excessive electrons from being discharged from a floating gate during erasure, by constituting a memory cell by providing erasure gates successively to the floating gate of a double gate type MOST. CONSTITUTION:A memory matrix of memory cells M each consisting of a control gate CG, an erasure gate EG, a floating gate FG, a source S, and a drain D has row lines 44 and erasure lines 48 as shown in a figure. Further, a means of setting the potential of each row line 44 to an earth potential or the starting threshold voltage of each cell during erasure and another means of selecting some cells M in one column simultaneously and giving a prescribed potential difference between the source and drain of each cell are provided. Furthermore, a means of applying the erasure line 48 of said selected column during the erasure and a means of detecting the source-drain current of each cell in the selected column and stopping the application of the erasure voltage to the erasure line 48 when detecting the current are provided.
JP617281A 1981-01-19 1981-01-19 Semiconductor storage device Granted JPS57120296A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP617281A JPS57120296A (en) 1981-01-19 1981-01-19 Semiconductor storage device
US06/320,937 US4437174A (en) 1981-01-19 1981-11-13 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP617281A JPS57120296A (en) 1981-01-19 1981-01-19 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS57120296A true JPS57120296A (en) 1982-07-27
JPS6130351B2 JPS6130351B2 (en) 1986-07-12

Family

ID=11631124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP617281A Granted JPS57120296A (en) 1981-01-19 1981-01-19 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS57120296A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02113495A (en) * 1988-10-21 1990-04-25 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02113495A (en) * 1988-10-21 1990-04-25 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPS6130351B2 (en) 1986-07-12

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