JPH02113495A - Semiconductor device - Google Patents

Abstract

PURPOSE:To stably set the threshold voltage of an erasing memory transistor TR by providing a dummy memory TR, a current detecting circuit, and a means which stops the erasing operation by the output of this circuit. CONSTITUTION:A memory TR M1 and a dummy memory TR Md1 are written in the initial state, and a threshold voltage VT of the memory TR is 0.8V. When an erasing signal Erase is switched from the low level to the high level and the erasing operation is started, an erasing signal generating circuit output voltage VE is switched from the low level to the high level, and a voltage VS is raised to +15V from 0V, and voltages VX and VR are equal to 0V and 2V respectively, and +15V, 0V, +15V, and +2V are impressed to the source of the TR M1, its control gate, the source of the TR Md1, and its control gate respectively, and TRs M1 and Md1 start erasing. At this time, the TR Md1 is turned on and its current is detected by a current detecting circuit A2. Thus, the circuit A2 drives the erasing signal generating circuit to stop the erasing operation. Consequently, TRs M1 and Md1 complete the erasing operation with 2V voltage VT, and the voltage VT is not reduced to 0V or lower.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to an erase circuit in a nonvolatile semiconductor device having a floating gate and capable of being electrically written and erased.

[Conventional technology]

Conventionally, an insulated gate field effect memory transistor (hereinafter referred to as a memory transistor), which is a nonvolatile semiconductor memory element having a floating gate and which can be electrically written and erased, has been described, for example, in the US Electronics magazine, 1980, 2.
As described in pages 113 to 117 of the May 28th issue, it is composed of two transistor elements: a selection transistor and a memory transistor. Furthermore, recently, in order to achieve higher density, a method has been proposed, for example, in IEEE 15SC01988 P133~, in which the selection transistor is omitted and the memory transistor is used as a single transistor element. FIG. 2 is a cross-sectional view of the structure of this memory transistor, in which a floating gate 2 is formed between a control gate 1 and a P-type semiconductor substrate 6 with an insulating film 3 interposed therebetween, and a drain 4
and a source 5 are formed on the substrate. Next, the basic operation of this memory transistor will be explained. First, writing to the memory transistor is performed as follows. When writing to drain 4 in accordance with the write information, a high voltage (+
12V) or OV is applied in the case of write inhibition, a high voltage (+12V) is applied to the control gate 1, and 0■ is applied to the source 5. When writing, a high voltage is applied to the drain and control gate, so hot electrons generated near the drain are captured by the floating gate, and electrons are accumulated in the floating gate, making the potential of the floating gate negative. When Ov is applied to the drain, no electrons are injected into the floating gate even if a high voltage (+12V) is applied to the control gate. This operation is the same as the widely known write operation of EPROM. In this way, a write operation is realized.

Next, the erase operation will be explained.

For erasing, Ov is applied to the control gate, and high voltage (+12V) is applied to the source.
is applied to generate a high electric field between the source and the floating gate.
-Nl- This is achieved by drawing electrons from the floating gate to the source using a channel current. At this time, the drain is open,
Any potential such as OV or positive potential may be used. A read operation is realized by applying a read voltage to the control gate to detect the state (II) of the floating gate of the memory transistor written or erased in this way and detecting the presence or absence of current flowing between the drain and source. . That is, when writing is performed and the potential of the floating gate is "negative", no current flows; in a state where no writing is performed or an erased state, the potential of the floating gate becomes "positive" and current flows.

[Problem to be solved by the invention]

In the above-mentioned conventional memory transistor, electrons are emitted from the floating gate to the source during the erase operation, and the potential of the floating gate becomes a positive potential. However, even after the desired erase is achieved, if the erase operation continues, the potential of the floating gate decreases. The positive potential further increases and the threshold voltage seen from the control gate becomes less than Ov, that is, depletion. When configuring a matrix of memory transistors with this characteristic, a plurality of memory transistors are usually connected in parallel with a common drain connected to the digit line, but when one memory transistor is selected for reading, the other memory transistor is If so, a problem arises in that reading from one memory transistor becomes impossible. In other words, one memory transistor is written to and the other memory transistor is connected in parallel to what should be 'off' in order to read this information. The information of one memory transistor seen from
n", causing information malfunction. The means to solve this problem are as follows. The process manufacturing conditions should be adjusted so that the threshold voltage of the memory transistor does not become depleted even after erasing. For example, ions are implanted into the channel region directly below the floating gate of the memory transistor to raise the threshold voltage of the memory transistor to 4V. Even if the threshold voltage decreases from 4V, it is difficult to fall below Ov.However, the drawback of this method is that the current flowing between the drain and source of the memory transistor during selective readout is small.In other words, when the readout voltage is 5V, Threshold 4■ Since the potential difference is only 1V, the ON current I of the memory transistor
on becomes below IOMA. Further, even if the threshold value is raised to 4V, there is a drawback that it is difficult to go below Ov when erased, but it becomes below Ov when erased for a long time, and it is not a fundamental solution. As described above, this memory transistor has the disadvantage that it is difficult to realize stable characteristics.

[Means to solve the problem]

A semiconductor device of the present invention includes an insulated gate field effect memory transistor having a floating gate and electrically writable and erasable, and a pseudo memory transistor having the same configuration as the memory transistor, and a source to drain of the pseudo memory transistor. A current detection circuit is provided for detecting the presence or absence of a current flowing through the memory transistor, and is connected to the drain of the pseudo memory transistor, and applies a high voltage to the sources of each of the memory transistor and the pseudo memory transistor during an erase operation, and applies a high voltage to the source of each of the memory transistor and the pseudo memory transistor. and means for stopping the erasing operation when current flows from the source to the drain of the pseudo memory transistor. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. A current detection circuit A2 is provided to detect the presence or absence of a current flowing from the source to the drain of the pseudo memory transistors Mdl and Mdl, which have the same configuration as the insulated gate field effect memory transistor M1 having a floating gate and which can be electrically written and erased, This circuit is connected to the drain of Mdl, and a source voltage circuit applies a high voltage vs to the sources of M1 and Mdl during consumption operation, and a voltage V8 (O
The voltage VR(2) applied to the control gate of Mdl is higher than the voltage VR(2
Pseudo control gate voltage circuit for increasing Md
When a current flows from the source to the drain of I, the erase stop signal V s t op changes from "L" to "H" to stop the erase signal generating circuit and stop the erase operation.

Further, write circuits for realizing writing are connected to the drains of Ml and Md1, respectively. Further, in order to realize the read operation of M1, the sense amplifier circuit A1 is connected to the drain of M1. The erase signal generation circuit output v8 receives the erase signals E rase and V s t op as inputs.

Next, the flow of the erase operation will be explained. Assume that in the initial state, data has been written to the memory transistors M1 and MdH1, and the threshold voltage vT of the memory transistors is +8V. Next, the erase signal E rase is
→ When it becomes ``H'' and the erase operation starts, v8 becomes ILII.
→“H”, v3 is ov-+15V, VX=OV, VR=
2VE, +15V to 7-s of Ml, OV to control gate
, +2V is applied to the control gate of +15V to the source of Md 1 and Ml.

Mdl begins erasing. The electrons accumulated in the floating gates of Ml and Mdl flow to the source, and ■
A decreases from 8V and approaches 0■.

At this time, a voltage of 2■ is applied to the control gate of Mdl, so when V of Mdl becomes 2V or less, Mdl becomes "o".
At n''', current begins to flow from the source to the drain of Mdl, and A2 detects this current.

As a result, A2 changes the output V s t op to IIL”→
II HII and drive the erase signal generation circuit to v8
II HII → “L”. v2 is “L”
As a result, the erase operation is stopped and Vs changes from 15V to Ov. Due to the action of A1, erasure is completed with vT of Ml and Mdl each being 2v, and when the erasing operation is performed, ①A can always be set to 2v, and vT does not become less than Ov.

〔Effect of the invention〕

As explained above, the present invention provides a pseudo memory transistor, a current detection circuit, and a means for stopping the erase operation using the output of the circuit, thereby making it possible to stably set the threshold voltage of the memory transistor during erasing, thereby increasing the threshold voltage. Change the voltage to “negative”
It has the effect of making it possible to remove the negative effects caused by

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a structural sectional view of a memory transistor used in the present invention. ■...Control gate, 2...Floating gate, 3...Insulating film, 4, 5...Drain, source, 6... semiconductor substrate. Agent Patent Attorney Susumu Uchihara ERASE Figure 2

Claims (1)

[Claims] In a semiconductor device having a floating gate and having an electrically writable and erasable insulated gate field effect memory transistor as a memory element, a pseudo memory element having the same configuration as the memory element and a source to drain of the pseudo memory element are provided. A current detection circuit for detecting the presence or absence of a flowing current is provided, and the circuit is connected to the drain of the pseudo memory element, and during an erase operation, a high voltage is applied to the sources of the memory element and the pseudo memory element, and the memory An erasing means sets the voltage applied to the control gate of the pseudo memory element higher than the voltage applied to the control gate of the element, and when a current flows from the source to the drain of the pseudo memory element, the current detection circuit performs an erasing operation. A semiconductor device characterized in that it is provided with means for stopping.