JPS57111872A - List processing system - Google Patents

List processing system

Info

Publication number
JPS57111872A
JPS57111872A JP18821780A JP18821780A JPS57111872A JP S57111872 A JPS57111872 A JP S57111872A JP 18821780 A JP18821780 A JP 18821780A JP 18821780 A JP18821780 A JP 18821780A JP S57111872 A JPS57111872 A JP S57111872A
Authority
JP
Japan
Prior art keywords
cpu20
processor
bmm21
bmm
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18821780A
Other languages
Japanese (ja)
Other versions
JPS6122824B2 (en
Inventor
Takeshi Shinoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18821780A priority Critical patent/JPS57111872A/en
Publication of JPS57111872A publication Critical patent/JPS57111872A/en
Publication of JPS6122824B2 publication Critical patent/JPS6122824B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE:To decrease the time of assignment that causes a problem with the software, by collecting the idle cells when no unused storage region exists any more. CONSTITUTION:A bit map memory (BMM) 21 in which mark bits are collected is prepared, and a BMM processor 21 is provided independently of a CPU20 to retrieve an unused cell which is used for the process of the memory 21. The BMM21 receives the access from both the CPU20 and the BMM processor 22 as a hardware. In case a program is running at the CPU20, the BMM21 gives an access to only a cell memory 10 through the processor 22. The processor 22 is discontinued during the collection of the garbage to be accessed from only the CPU20. As a result, no access conflict is caused at all for the BMM21.
JP18821780A 1980-12-27 1980-12-27 List processing system Granted JPS57111872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18821780A JPS57111872A (en) 1980-12-27 1980-12-27 List processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18821780A JPS57111872A (en) 1980-12-27 1980-12-27 List processing system

Publications (2)

Publication Number Publication Date
JPS57111872A true JPS57111872A (en) 1982-07-12
JPS6122824B2 JPS6122824B2 (en) 1986-06-03

Family

ID=16219810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18821780A Granted JPS57111872A (en) 1980-12-27 1980-12-27 List processing system

Country Status (1)

Country Link
JP (1) JPS57111872A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0731619B2 (en) * 1985-01-11 1995-04-10 バロ−ス・コ−ポレ−ション System allocator for reduced processors that evaluate programs stored as binary directed graphs using variable-free functional language code
JPH083801B2 (en) * 1985-01-11 1996-01-17 バロ−ス・コ−ポレ−ション System allocator for a reduced processor that evaluates programs stored as binary directed graphs using frequency-free functional language code

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0731619B2 (en) * 1985-01-11 1995-04-10 バロ−ス・コ−ポレ−ション System allocator for reduced processors that evaluate programs stored as binary directed graphs using variable-free functional language code
JPH083801B2 (en) * 1985-01-11 1996-01-17 バロ−ス・コ−ポレ−ション System allocator for a reduced processor that evaluates programs stored as binary directed graphs using frequency-free functional language code

Also Published As

Publication number Publication date
JPS6122824B2 (en) 1986-06-03

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