JPS57111753A - Display system - Google Patents

Display system

Info

Publication number
JPS57111753A
JPS57111753A JP55185399A JP18539980A JPS57111753A JP S57111753 A JPS57111753 A JP S57111753A JP 55185399 A JP55185399 A JP 55185399A JP 18539980 A JP18539980 A JP 18539980A JP S57111753 A JPS57111753 A JP S57111753A
Authority
JP
Japan
Prior art keywords
address
scan
side end
latch
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55185399A
Other languages
Japanese (ja)
Inventor
Taiji Nosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55185399A priority Critical patent/JPS57111753A/en
Publication of JPS57111753A publication Critical patent/JPS57111753A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To display a state even if a service processor has been downed, by converting a counting value to a scan-out address having a different value, in a system for displaying a state of a latch and a register in a processing device. CONSTITUTION:In case it is desired to scan out the inside of a block 12, a numerical value assigned to the block 12 is set to a fixed part 7a of an address counter 7 by a block setting circuit 9, and a counter part 7b is started. A counting value of the address counter 7 is inputted to a memory 4 as address information, and scan-out addresses a1, a2-an are generated. Subsequently, at first, status information of a latch is read out by being designated by the address a1, and is superposed on a scan-out data line (ls) of the right side end. In this case, when a signal of the data output line of the right side end becomes on, a latch state of the address a1 is displayed by a light emission diode 1 of the right side end. Subsequently, a latch state of the address a2 is read out, and is displayed by the second diode 1 from the right side end.
JP55185399A 1980-12-29 1980-12-29 Display system Pending JPS57111753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55185399A JPS57111753A (en) 1980-12-29 1980-12-29 Display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55185399A JPS57111753A (en) 1980-12-29 1980-12-29 Display system

Publications (1)

Publication Number Publication Date
JPS57111753A true JPS57111753A (en) 1982-07-12

Family

ID=16170111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55185399A Pending JPS57111753A (en) 1980-12-29 1980-12-29 Display system

Country Status (1)

Country Link
JP (1) JPS57111753A (en)

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