JPS5710929A - Exposing method by electron beam - Google Patents

Exposing method by electron beam

Info

Publication number
JPS5710929A
JPS5710929A JP8547680A JP8547680A JPS5710929A JP S5710929 A JPS5710929 A JP S5710929A JP 8547680 A JP8547680 A JP 8547680A JP 8547680 A JP8547680 A JP 8547680A JP S5710929 A JPS5710929 A JP S5710929A
Authority
JP
Japan
Prior art keywords
marks
mark
hand corner
wafer
fields
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8547680A
Other languages
Japanese (ja)
Other versions
JPS6235262B2 (en
Inventor
Hitoshi Takemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jeol Ltd
Original Assignee
Jeol Ltd
Nihon Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jeol Ltd, Nihon Denshi KK filed Critical Jeol Ltd
Priority to JP8547680A priority Critical patent/JPS5710929A/en
Publication of JPS5710929A publication Critical patent/JPS5710929A/en
Publication of JPS6235262B2 publication Critical patent/JPS6235262B2/ja
Granted legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3174—Particle-beam lithography, e.g. electron beam lithography

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To reduce the number of marks by a method wherein an exposing region is divided into a plurality of fields, a mark is put on a top left-hand corner of the first drawing region, the deflection width of the electron beams is obtained on the basis of the amount of movement at the time when the regions move so that the mark reaches a bottom right-hand corner, and the regions are exposed successively. CONSTITUTION:Marks XA, XB, YA, YB are put previously on a peripheral section of a wafer 5, and the wafer is set on a stage on the basis of the coordinate data of the marks. Each chip of the wafer is divided into fields such as nine fields F1-F9 before exposing, the crossed mark M is put previously on the top left-hand corner of the drawing staring field, the amounts LX, LY of the movement of the stage in the case when the mark is moved to the bottom right-hand corner first are measured beforhand, the stage is shifted only by the amounts of movement when the drawing regions are transferred, and the deflection width of the electron beams is decided. Accordingly, the marks put on the chips are reduced, and a design for a circuit is simplified.
JP8547680A 1980-06-24 1980-06-24 Exposing method by electron beam Granted JPS5710929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8547680A JPS5710929A (en) 1980-06-24 1980-06-24 Exposing method by electron beam

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8547680A JPS5710929A (en) 1980-06-24 1980-06-24 Exposing method by electron beam

Publications (2)

Publication Number Publication Date
JPS5710929A true JPS5710929A (en) 1982-01-20
JPS6235262B2 JPS6235262B2 (en) 1987-07-31

Family

ID=13859955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8547680A Granted JPS5710929A (en) 1980-06-24 1980-06-24 Exposing method by electron beam

Country Status (1)

Country Link
JP (1) JPS5710929A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205767A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Data processor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0320669A (en) * 1989-05-20 1991-01-29 Sanyo Electric Co Ltd Speed display apparatus for bicycle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205767A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Data processor

Also Published As

Publication number Publication date
JPS6235262B2 (en) 1987-07-31

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