JPS57106152A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57106152A
JPS57106152A JP18353180A JP18353180A JPS57106152A JP S57106152 A JPS57106152 A JP S57106152A JP 18353180 A JP18353180 A JP 18353180A JP 18353180 A JP18353180 A JP 18353180A JP S57106152 A JPS57106152 A JP S57106152A
Authority
JP
Japan
Prior art keywords
layer
wire
semiconductor substrate
reducing
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18353180A
Other languages
Japanese (ja)
Inventor
Shigeru Koshimaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP18353180A priority Critical patent/JPS57106152A/en
Publication of JPS57106152A publication Critical patent/JPS57106152A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To enable the high speed operation of a semiconductor device in a wire of the device by reducing the parasitic capacity between a semiconductor substrate and the wire. CONSTITUTION:The first and second wire layers 6, 7 are laminated via an interlayer insulating film 5 on a semiconductor substrate 4. The first layer 6 is formed narrower than the layer 7 by the width B, thereby reducing the parasitic capacity with respect to the semiconductor substrate of the entire wire formed of the first and second layers 6, 7. In order to reduce the width of the first layer 6 as compared with the second layer 7, the layer 6 is formed of polycrystalline silicon, and the second layer 7 is formed of aluminum. Then, the layer 7 is etched, the layer 6 is then overetched by wet etching.
JP18353180A 1980-12-24 1980-12-24 Semiconductor device Pending JPS57106152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18353180A JPS57106152A (en) 1980-12-24 1980-12-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18353180A JPS57106152A (en) 1980-12-24 1980-12-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57106152A true JPS57106152A (en) 1982-07-01

Family

ID=16137455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18353180A Pending JPS57106152A (en) 1980-12-24 1980-12-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57106152A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6084840A (en) * 1983-10-14 1985-05-14 Seiko Epson Corp Multilayer interconnection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6084840A (en) * 1983-10-14 1985-05-14 Seiko Epson Corp Multilayer interconnection

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