JPS5710518A - Controlling method for electric charge transfer delay line - Google Patents

Abstract

PURPOSE:To avoid the effect due to an input signal, by using a compensating OCD delay line having equal input and output characteristics as that of a main CCD delay line to control the bias charge of the main CCD delay line. CONSTITUTION:An input signal 14 superimposed with a bias voltage V1 is applied to an input gate G2 of a main CCD delay line 15 and a DC voltage equal to the bias voltage V1 is applied to an input gate G2C of a compensating CCD delay line 16. Input diodes ID and IDC for the main and compensating CCD delay lines are commonly connected and a sampling pulse 18 is applied with each pulse of a clock pulse commonly driving the main and compensating delay lines. Thus, an electric charge corresponding to the potential difference between input gates G1C and G2C is inputted to the compensating CCD delay line. When the output 20 is introduced to a control circuit 23 and the voltage for the input gates G1 and G1C is commonly controlled so that the value is constant at all times, the output 20 is controlled to a given value and the bias charge on the main CCD delay line 15 can be controlled to a given value.