JPS57105057A - Address system of external storage device - Google Patents
Address system of external storage deviceInfo
- Publication number
- JPS57105057A JPS57105057A JP18132380A JP18132380A JPS57105057A JP S57105057 A JPS57105057 A JP S57105057A JP 18132380 A JP18132380 A JP 18132380A JP 18132380 A JP18132380 A JP 18132380A JP S57105057 A JPS57105057 A JP S57105057A
- Authority
- JP
- Japan
- Prior art keywords
- read
- circuits
- write
- signals
- track
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To realize the effecive use of a data part, by selecting the output of a circuit which produces the read/write signals for the 1st and 2nd formats by means of the highest order bit of a track address and accordingly realizing the read or write in different formats with ever track. CONSTITUTION:Read/write gate signal generating circuits 1 and 3 plus decoder circuits 2 and 4 are provided to formatsIand II respectively. Then read/write signals 15 and 17 corresponding to each sector are produced from the circuits 1 and 3 by the internal clock of an external storage device. At the same time, the circuits 2 and 4 deliver decoder 4-bit and 8-bit outputs 16 and 18 by an address that designates a data sector given from outside. The coincidence is detected through coincidence detecting circuits 5 and 6 between the decoder outputs 16/18 and the signals 15/17 respectively. Then format selection signals 19 and 21 are applied to a logical circuit which uses a format selection signal 20 as an input. Thus a read/write signal 22 produced by the formats different with each track is delivered.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18132380A JPS57105057A (en) | 1980-12-23 | 1980-12-23 | Address system of external storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18132380A JPS57105057A (en) | 1980-12-23 | 1980-12-23 | Address system of external storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57105057A true JPS57105057A (en) | 1982-06-30 |
Family
ID=16098670
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18132380A Pending JPS57105057A (en) | 1980-12-23 | 1980-12-23 | Address system of external storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57105057A (en) |
-
1980
- 1980-12-23 JP JP18132380A patent/JPS57105057A/en active Pending
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