JPS57103196A - Shift register - Google Patents

Shift register

Info

Publication number
JPS57103196A
JPS57103196A JP55177097A JP17709780A JPS57103196A JP S57103196 A JPS57103196 A JP S57103196A JP 55177097 A JP55177097 A JP 55177097A JP 17709780 A JP17709780 A JP 17709780A JP S57103196 A JPS57103196 A JP S57103196A
Authority
JP
Japan
Prior art keywords
register file
optional
shift
adder
specifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55177097A
Other languages
Japanese (ja)
Inventor
Hidekiyo Ozawa
Mikio Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55177097A priority Critical patent/JPS57103196A/en
Publication of JPS57103196A publication Critical patent/JPS57103196A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/38—Digital stores in which the information is moved stepwise, e.g. shift registers two-dimensional, e.g. horizontal and vertical shift registers

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To reduce occupation area by enabling a shift by an optional number of stages, by providing a counter for specifying the readout address of a register file constituted by integrating registers and an adder which generates a write address by using a count value and an optional number. CONSTITUTION:A register file 2 which is constituted by integrating registers and performs writing operation and reading operation simultaneously in the same cycle, a counter 4 for specifying the readout address RA of the register file 2, and an adder 6 which generates the write address WA of the register file 2 by adding the value of the couter 4 and an optional supplied number (k) are provided. Consequently, a shift by an optional number (k) of stages is enabled and occupation area is reduced.
JP55177097A 1980-12-17 1980-12-17 Shift register Pending JPS57103196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55177097A JPS57103196A (en) 1980-12-17 1980-12-17 Shift register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55177097A JPS57103196A (en) 1980-12-17 1980-12-17 Shift register

Publications (1)

Publication Number Publication Date
JPS57103196A true JPS57103196A (en) 1982-06-26

Family

ID=16025078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55177097A Pending JPS57103196A (en) 1980-12-17 1980-12-17 Shift register

Country Status (1)

Country Link
JP (1) JPS57103196A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605499A (en) * 1983-06-23 1985-01-12 Fujitsu Ltd Resetting system of register file

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5012640A (en) * 1973-06-04 1975-02-08
JPS52154311A (en) * 1976-06-17 1977-12-22 Matsushita Electric Ind Co Ltd Fifo queue processing system
JPS5391540A (en) * 1977-01-24 1978-08-11 Anritsu Electric Co Ltd Digital delay unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5012640A (en) * 1973-06-04 1975-02-08
JPS52154311A (en) * 1976-06-17 1977-12-22 Matsushita Electric Ind Co Ltd Fifo queue processing system
JPS5391540A (en) * 1977-01-24 1978-08-11 Anritsu Electric Co Ltd Digital delay unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605499A (en) * 1983-06-23 1985-01-12 Fujitsu Ltd Resetting system of register file
JPH0474799B2 (en) * 1983-06-23 1992-11-27

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