JPS5692626A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS5692626A
JPS5692626A JP16989579A JP16989579A JPS5692626A JP S5692626 A JPS5692626 A JP S5692626A JP 16989579 A JP16989579 A JP 16989579A JP 16989579 A JP16989579 A JP 16989579A JP S5692626 A JPS5692626 A JP S5692626A
Authority
JP
Japan
Prior art keywords
inquiry
input
scanning
output
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16989579A
Other languages
Japanese (ja)
Inventor
Yukio Taniyama
Tetsuo Nagabori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16989579A priority Critical patent/JPS5692626A/en
Publication of JPS5692626A publication Critical patent/JPS5692626A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the instruction start time of input/output control device, by scanning and referring the inquiry memory before the end of operation of I/O is informed to CPU, and providing the means to store the content when inquiry is made.
CONSTITUTION: A scanning circuit II12 is started with a machine cycle and signal, and the input of a multiplexer MPX3, i.e., the scanning of the content of an inquiry memory 1 is made before the information of CPU. As a result, if at least one inquiry state is present in the memory 1, FF15 is set and the presence of inquiry is stored. Thus, an AND gate 9 is closed and the input and output start instruction is waited. After that, FF8 is set with the scanning end signal I of a scanning circuit I11, FF15 is reset with the output Q, the gate 9 is opened, the machine cycle start signal is formed, and the machine cycle start circuit 10 is started. If no inquiry is made, FF15 is not set, the output Q of FF8 is 0, the gate 9 is opened, the I/O controller is immediately operated and the instruction start time is reduced.
COPYRIGHT: (C)1981,JPO&Japio
JP16989579A 1979-12-26 1979-12-26 Input/output control system Pending JPS5692626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16989579A JPS5692626A (en) 1979-12-26 1979-12-26 Input/output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16989579A JPS5692626A (en) 1979-12-26 1979-12-26 Input/output control system

Publications (1)

Publication Number Publication Date
JPS5692626A true JPS5692626A (en) 1981-07-27

Family

ID=15894946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16989579A Pending JPS5692626A (en) 1979-12-26 1979-12-26 Input/output control system

Country Status (1)

Country Link
JP (1) JPS5692626A (en)

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