JPS5690643A - Digital multiplexer - Google Patents

Digital multiplexer

Info

Publication number
JPS5690643A
JPS5690643A JP16891879A JP16891879A JPS5690643A JP S5690643 A JPS5690643 A JP S5690643A JP 16891879 A JP16891879 A JP 16891879A JP 16891879 A JP16891879 A JP 16891879A JP S5690643 A JPS5690643 A JP S5690643A
Authority
JP
Japan
Prior art keywords
circuit
pulse
supplied
buffer memory
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16891879A
Other languages
Japanese (ja)
Inventor
Hideo Tatsuno
Kohei Otake
Seiichiro Kozuka
Seiichi Yamano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP16891879A priority Critical patent/JPS5690643A/en
Publication of JPS5690643A publication Critical patent/JPS5690643A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To simplify the constitution of device and to shorten information delay time, reducing the capacity of a buffer memory for conversion. CONSTITUTION:A multiplex signal inputted from input terminal H/IN is separated by separating circuit SEP into signals of many channels, which are supplied to buffer memory MEM1. A readout output from memory MEM1 is given an appended burst signal pulse by pulse inserting circuit P1 and then sent to subscriber's line terminal TER via unipolar/bipolar conversion circuit UB and power separating filter PSF. The signal arriving at terminal TER, on the other hand, is supplied to bipolar/ unipolar conversion circuit BU via filter PSF and equalizer EQ. From this signal, a burst signal pulse is removed by pulse separating circuit P2 and the remainder is supplied to buffer memory MEM2 via delay inserting-extracting circuit D. The output of it is multiplexed by multiplexing circuit MPX.
JP16891879A 1979-12-24 1979-12-24 Digital multiplexer Pending JPS5690643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16891879A JPS5690643A (en) 1979-12-24 1979-12-24 Digital multiplexer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16891879A JPS5690643A (en) 1979-12-24 1979-12-24 Digital multiplexer

Publications (1)

Publication Number Publication Date
JPS5690643A true JPS5690643A (en) 1981-07-22

Family

ID=15876964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16891879A Pending JPS5690643A (en) 1979-12-24 1979-12-24 Digital multiplexer

Country Status (1)

Country Link
JP (1) JPS5690643A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985003610A1 (en) * 1984-02-03 1985-08-15 Nippon Telegraph & Telephone Public Corporation Multi-phase synchronizing circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985003610A1 (en) * 1984-02-03 1985-08-15 Nippon Telegraph & Telephone Public Corporation Multi-phase synchronizing circuit
US4682327A (en) * 1984-02-03 1987-07-21 Nippon Telegraph And Telephone Corp. Polyphase phase lock oscillator

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