JPS5687127A - Connecting system for input/output control device - Google Patents

Connecting system for input/output control device

Info

Publication number
JPS5687127A
JPS5687127A JP16460479A JP16460479A JPS5687127A JP S5687127 A JPS5687127 A JP S5687127A JP 16460479 A JP16460479 A JP 16460479A JP 16460479 A JP16460479 A JP 16460479A JP S5687127 A JPS5687127 A JP S5687127A
Authority
JP
Japan
Prior art keywords
circuit
output control
cpu
process request
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16460479A
Other languages
Japanese (ja)
Inventor
Ryoji Miwa
Tatsuo Ushiki
Koichi Onishi
Naotoshi Ukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP16460479A priority Critical patent/JPS5687127A/en
Publication of JPS5687127A publication Critical patent/JPS5687127A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize an increment for the number of high-speed input/output control devices which can be connected to the CPU, by providing a simple additional circuit without changing the circuits within the CPU.
CONSTITUTION: The process request given from the input/output control device 2 or 7 is displayed at the corresponding process request display circuit 16 or 17 in the adaptor circuit 8. The logic sum is secured at the OR circuit 18 for the outputs of the circuits 16 and 17 to be supplied to the process request display circuit 11. Furthermore the displayed output of the circuit 16 or 17 is supplied to the low-speed data transfer circuit 15 of the CPU1 via the bus circuit 6. Thus the CPU1 reads the output periodically and based on the program in order to decide whether the device 2 or 7 has delivered the process request. As a result, an increment is ensured for the number of high-speed input/output control devices which can be connected to the CPU without changing the circuits in the CPU but by just adding a simple circuit.
COPYRIGHT: (C)1981,JPO&Japio
JP16460479A 1979-12-18 1979-12-18 Connecting system for input/output control device Pending JPS5687127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16460479A JPS5687127A (en) 1979-12-18 1979-12-18 Connecting system for input/output control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16460479A JPS5687127A (en) 1979-12-18 1979-12-18 Connecting system for input/output control device

Publications (1)

Publication Number Publication Date
JPS5687127A true JPS5687127A (en) 1981-07-15

Family

ID=15796328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16460479A Pending JPS5687127A (en) 1979-12-18 1979-12-18 Connecting system for input/output control device

Country Status (1)

Country Link
JP (1) JPS5687127A (en)

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