JPS5685172A - Rewriting system pseudoerror - Google Patents

Rewriting system pseudoerror

Info

Publication number
JPS5685172A
JPS5685172A JP16249279A JP16249279A JPS5685172A JP S5685172 A JPS5685172 A JP S5685172A JP 16249279 A JP16249279 A JP 16249279A JP 16249279 A JP16249279 A JP 16249279A JP S5685172 A JPS5685172 A JP S5685172A
Authority
JP
Japan
Prior art keywords
memory
address
data
error
pseudodisk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16249279A
Other languages
Japanese (ja)
Other versions
JPS5918748B2 (en
Inventor
Yuta Adachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54162492A priority Critical patent/JPS5918748B2/en
Publication of JPS5685172A publication Critical patent/JPS5685172A/en
Publication of JPS5918748B2 publication Critical patent/JPS5918748B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To realize a high efficiency for a defect producing system, by shunting the reading data of an IC memory to a buffer register in case an error data is written into the IC memory due to an defective pseudomedium and then carrying out a rewriting to the IC memory during the retrial.
CONSTITUTION: The pseudodisk device 1 consists of the IC memory 3 replaced with a memory medium and the pseudodisk unit 2 which perform a pseudocontrol using the memory 3 as a disk unit. Thus during the writing via the channel device CHC, the data stored in the memory 3 is stored temporarily in the buffer register R2 when a coincidence is obtained between the error address registers R4/R4' and the address counter AC which counts the clock signals to use them for the medium address. Then an optional error data is written into an optional error address. For the retrial, the contents of the register R2 is rewritten into the memory 3.
COPYRIGHT: (C)1981,JPO&Japio
JP54162492A 1979-12-14 1979-12-14 Pseudo-error rewriting method Expired JPS5918748B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54162492A JPS5918748B2 (en) 1979-12-14 1979-12-14 Pseudo-error rewriting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54162492A JPS5918748B2 (en) 1979-12-14 1979-12-14 Pseudo-error rewriting method

Publications (2)

Publication Number Publication Date
JPS5685172A true JPS5685172A (en) 1981-07-11
JPS5918748B2 JPS5918748B2 (en) 1984-04-28

Family

ID=15755640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54162492A Expired JPS5918748B2 (en) 1979-12-14 1979-12-14 Pseudo-error rewriting method

Country Status (1)

Country Link
JP (1) JPS5918748B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6421544A (en) * 1987-07-17 1989-01-24 Hitachi Ltd Fault generation system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6421544A (en) * 1987-07-17 1989-01-24 Hitachi Ltd Fault generation system

Also Published As

Publication number Publication date
JPS5918748B2 (en) 1984-04-28

Similar Documents

Publication Publication Date Title
EP0031499A3 (en) Data processing apparatus adapted for memory readback checking
DE3688136D1 (en) METHOD FOR TESTING AND SETTING DATA INTO A DATA RECORD ON A DISK IN AN ATOMAR INPUT / OUTPUT OPERATION.
JPS5530730A (en) Data processor
JPS57113162A (en) High-speed external storage device
DE3485130D1 (en) METHOD FOR OPERATING A PAIR OF MEMORY BLOCKS OPERATING IN NORMAL OPERATING TIME.
JPS5685172A (en) Rewriting system pseudoerror
JPS5576475A (en) Card processor
JPS5750380A (en) Writing method of buffer storage device
JPS578829A (en) Input and output controller
JPS56159747A (en) Program testing device
JPS5654698A (en) Test method of memory device
JPS5528501A (en) Test system for memory device
JPS54142942A (en) Address checking system
JPS5447446A (en) Magnetic disc control unit
JPS5587261A (en) Cartridge transfer confirmation system
JPS57112177A (en) Frame signal generating device
JPS57174751A (en) Data storage device
JPS57212606A (en) Magnetic card recording system
JPS5644187A (en) Write check system of bubble memory
JPS56124199A (en) Data processing device
JPS5453839A (en) Magnetic bubble memory
JPS5481036A (en) Magnetic bubble memory unit
JPS57103531A (en) Memory controller
JPS5481809A (en) Magnetic tape memory system
JPS5423513A (en) Magnetic disc controller